PIC16F1519 View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16F1519

28/40/44-Pin Flash Microcontrollers with XLP Technology

Microchip Technology 

TABLE 3-3: PIC16(L)F1516/7 MEMORY MAP

BANK 0

BANK 1

BANK 2

000h

Core Registers

(Table 3-2)

080h

Core Registers

(Table 3-2)

100h

Core Registers

(Table 3-2)

00Bh

00Ch

00Dh

00Eh

00Fh

010h

011h

012h

013h

014h

015h

016h

017h

018h

019h

01Ah

01Bh

01Ch

01Dh

01Eh

PORTA

PORTB

PORTC

PORTD(1)

PORTE

PIR1

PIR2

—

—

TMR0

TMR1L

TMR1H

T1CON

T1GCON

TMR2

PR2

T2CON

—

—

08Bh

08Ch

08Dh

08Eh

08Fh

090h

091h

092h

093h

094h

095h

096h

097h

098h

099h

09Ah

09Bh

09Ch

09Dh

09Eh

TRISA

TRISB

TRISC

TRISD(1)

TRISE

PIE1

PIE2

—

—

OPTION_REG

PCON

WDTCON

—

OSCCON

OSCSTAT

ADRESL

ADRESH

ADCON0

ADCON1

10Bh

10Ch

10Dh

10Eh

10Fh

110h

111h

112h

113h

114h

115h

116h

117h

118h

119h

11Ah

11Bh

11Ch

11Dh

11Eh

LATA

LATB

LATC

LATD(1)

LATE(1)

—

—

—

—

—

BORCON

FVRCON

—

—

—

—

—

APFCON

—

01Fh

—

09Fh

—

11Fh

—

020h

0A0h

120h

General

Purpose

Register

80 Bytes

General

Purpose

Register

80 Bytes

General

Purpose

Register

80 Bytes

06Fh

070h

07Fh

Common RAM

0EFh

0F0h

0FFh

Common RAM

(Accesses

70h – 7Fh)

16Fh

170h

17Fh

Common RAM

(Accesses

70h – 7Fh)

Legend:

Note 1:

2:

= Unimplemented data memory locations, read as ‘0’.

PIC16(L)F1517 only.

PIC16F1516/7 only.

180h

18Bh

18Ch

18Dh

18Eh

18Fh

190h

191h

192h

193h

194h

195h

196h

197h

198h

199h

19Ah

19Bh

19Ch

19Dh

19Eh

19Fh

1A0h

1EFh

1F0h

1FFh

BANK 3

Core Registers

(Table 3-2)

ANSELA

ANSELB

ANSELC

ANSELD(1)

ANSELE(1)

PMADRL

PMADRH

PMDATL

PMDATH

PMCON1

PMCON2

VREGCON(2)

—

RCREG

TXREG

SPBRG

SPBRGH

RCSTA

TXSTA

BAUDCON

General

Purpose

Register

80 Bytes

Common RAM

(Accesses

70h – 7Fh)

200h

20Bh

20Ch

20Dh

20Eh

20Fh

210h

211h

212h

213h

214h

215h

216h

217h

218h

219h

21Ah

21Bh

21Ch

21Dh

21Eh

21Fh

220h

26Fh

270h

27Fh

BANK 4

Core Registers

(Table 3-2)

—

WPUB

—

—

WPUE

SSPBUF

SSPADD

SSPMSK

SSPSTAT

SSPCON1

SSPCON2

SSPCON3

—

—

—

—

—

—

—

—

General

Purpose

Register

80 Bytes

Common RAM

(Accesses

70h – 7Fh)

280h

28Bh

28Ch

28Dh

28Eh

28Fh

290h

291h

292h

293h

294h

295h

296h

297h

298h

299h

29Ah

29Bh

29Ch

29Dh

29Eh

29Fh

2A0h

2EFh

2F0h

2FFh

BANK 5

Core Registers

(Table 3-2)

—

—

—

—

—

CCPR1L

CCPR1H

CCP1CON

—

—

—

—

CCPR2L

CCPR2H

CCP2CON

—

—

—

—

—

General

Purpose

Register

80 Bytes

Common RAM

(Accesses

70h – 7Fh)

BANK 6

300h

Core Registers

(Table 3-2)

380h

30Bh

38Bh

30Ch

—

38Ch

30Dh

—

38Dh

30Eh

—

38Eh

30Fh

—

38Fh

310h

—

390h

311h

—

391h

312h

—

392h

313h

—

393h

314h

—

394h

315h

—

395h

316h

—

396h

317h

—

397h

318h

—

398h

319h

—

399h

31Ah

—

39Ah

31Bh

—

39Bh

31Ch

—

39Ch

31Dh

—

39Dh

31Eh

—

39Eh

31Fh

—

39Fh

320h General Purpose 3A0h

Register

32Fh

16 Bytes

330h

Unimplemented

Read as ‘0’

36Fh

3EFh

370h

37Fh

Common RAM

(Accesses

70h – 7Fh)

3F0h

3FFh

BANK 7

Core Registers

(Table 3-2)

—

—

—

—

—

—

—

—

IOCBP

IOCBN

IOCBF

—

—

—

—

—

—

—

—

—

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

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