PIC16F1519 View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16F1519

28/40/44-Pin Flash Microcontrollers with XLP Technology

Microchip Technology 

TABLE 3-5: PIC16(L)F1518/9 MEMORY MAP (CONTINUED)

BANK 8

BANK 9

BANK 10

BANK 11

BANK 12

BANK 13

BANK 14

BANK 15

400h

40Bh

40Ch

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

480h

48Bh

48Ch

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

500h

50Bh

50Ch

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

580h

58Bh

58Ch

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

600h

60Bh

60Ch

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

680h

68Bh

68Ch

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

700h

70Bh

70Ch

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

780h

78Bh

78Ch

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

41Fh

420h

46Fh

470h

47Fh

General

Purpose

Register

80 Bytes

Common RAM

(Accesses

70h – 7Fh)

49Fh

4A0h

4EFh

4F0h

4FFh

General

Purpose

Register

80 Bytes

Common RAM

(Accesses

70h – 7Fh)

51Fh

520h

56Fh

570h

57Fh

General

Purpose

Register

80 Bytes

Common RAM

(Accesses

70h – 7Fh)

59Fh

5A0h

5EFh

5F0h

5FFh

General

Purpose

Register

80 Bytes

Common RAM

(Accesses

70h – 7Fh)

61Fh

620h

64Fh

General Purpose

Register

48 Bytes

69Fh

6A0h

650h

66Fh

Unimplemented

Read as ‘0’

6EFh

670h

67Fh

Common RAM

(Accesses

70h – 7Fh)

6F0h

6FFh

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

71Fh

720h

76Fh

770h

77Fh

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

79Fh

7A0h

7EFh

7F0h

7FFh

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

BANK 16

BANK 17

BANK 18

BANK 19

BANK 20

BANK 21

BANK 22

BANK 23

800h

80Bh

80Ch

86Fh

870h

87Fh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

880h

88Bh

88Ch

8EFh

8F0h

8FFh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

900h

90Bh

90Ch

96Fh

970h

97Fh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

980h

98Bh

98Ch

9EFh

9F0h

9FFh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

A00h

A0Bh

A0Ch

A6Fh

A70h

A7Fh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

A80h

A8Bh

A8Ch

AEFh

AF0h

AFFh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

B00h

B0Bh

B0Ch

B6Fh

B70h

B7Fh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

B80h

B8Bh

B8Ch

BEFh

BF0h

BFFh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

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