DPL3520A View Datasheet(PDF) - Micronas
Part Name
Description
Manufacturer
DPL3520A Datasheet PDF : 56 Pages
| |||
PRELIMINARY DATA SHEET
Analog
Inputs
I2S Bus
Inputs
SCARTL
SCARTR
I2S1L
I2S1R
I2S2L
I2S2R
Prescale
Prescale
Prescale
Noise
Generator
Surround
Source
Matrix
Dolby
Pro Logic
or
Passive
or
Effect
L/L+C/PSL
R/R)C/PSR
C
S
C
SUB
Fig. 2–2: Firmware block diagram
DPL 35xxA
Channel1
Matrix
Channel2
Matrix
Equalizer or
Bass/Treble
Loudness
Spatial Effects
Bass,Treble
Loudness
Spatial Effects
Beeper
Bass,Treble
Loudness
Volume
Balance
Volume
Balance
SCART
Channel
Matrix
Volume
I2S1
Channel
Matrix
OUT1L
OUT1R
OUT2L
OUT2R
SCARTL
SCARTR
I2S1L
I2S1R
I2S2
Channel
Matrix
I2S2L
I2S2R
Channel 1
Output
Channel 2
Output
SCART
Output
I2S1
Output
I2S2
Output
Quasi-Peak
Channel
Matrix
Quasi-Peak
Detector
Quasi peak readout L
Quasi peak readout R
I2S1L
Internal signal lines
2.3. Features of the Analog Output Section
– channel 1 and 2: two pairs of 4-fold oversampled D/A-
converters
Output level per channel: max. 1.4 VRMS
Output resistance: max. 5 kΩ
S/N-Ratio: w85 dB at maximum volume; max. noise
voltage in mute mode: v3 µV (BW: 20 Hz...16 kHz)
– one pair of four-fold oversampled D/A-converters sup-
plying two selectable pairs of SCART-Outputs.
Output level per channel: max. 2 VRMS
Output resistance: max. 0.5 kΩ
S/N-Ratio: w85 dB (20 Hz ... 16 kHz)
2.4. SCART Switches
The analog input and output sections offer a wide range
of switching facilities, which are shown in Fig. 2–3.
The switches are controlled by the ACB bits defined in
the audio processing interface (see section 9. Program-
ming the DSP Part).
If the DPL is switched off by first pulling STANDBYQ low,
and then disconnecting the 5 V, but keeping the 8 V pow-
er supply (‘Standby’-mode), the switches S1, S2, and
S3 maintain their position and function. This facilitates
the copying from selected SCART-inputs to SCART-out-
puts in the TV-sets standby mode.
Micronas
SCART_IN
SC1_IN_L/R
2
MONO
2
SC2_IN_L/R
2
SC3_IN_L/R
2
from Audio Baseband
Processing (DFP)
SCARTL/R
D
2A
ACB[1:0]
00
to Audio Baseband
Processing (DFP)
01
A
D2
10
SCARTL/R
11 S1
ACB[3:2]
2
00
2
01
2
10
SCART_OUT
2
SC1_OUT_L/R
2
11 S2
ACB[5:4]
2
00
2
01
2
10 S3
2
SC2_OUT_L/R
Fig. 2–3: SCART-Switching Facilities
Bold lines determine the default configuration
In case of power-on start or starting from standby, the IC
switches automatically to the default configuration,
shown in Fig. 2–3. This takes place after the first I2C
transmission into the DFP part. By transmitting the ACB
register first, the default setting mode can be changed.
7
Share Link: 