ADF7021_06 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADF7021_06

High Performance Narrowband ISM Transceiver IC

Analog Devices 

Preliminary Technical Data

Parameter

Min

CHANNEL FILTERING

Adjacent Channel Rejection

(Offset = ±1 × IF Filter BW Setting)

Second Adjacent Channel Rejection

(Offset = ±2 × IF Filter BW Setting)

Third Adjacent Channel Rejection

(Offset = ±3 × IF Filter BW Setting)

Image Channel Rejection

Co-Channel Rejection

Wideband Interference Rejection

BLOCKING

±1 MHz

±5 MHz

±10 MHz

±10 MHz (High Linearity Mode)

Saturation (Maximum Input Level)

LNA Input Impedance

RECEIVE SIGNAL STRENGTH INDICATOR (RSSI)

Range at Input

Linearity

Absolute Accuracy

Response Time

PHASE-LOCKED LOOP (PLL)

VCO Gain

Phase Noise (In-Band)

Phase Noise (Out-of-Band)

Residual FM

PLL Settling

REFERENCE INPUT

Crystal Reference

External Oscillator

Load Capacitance

Crystal Start-Up Time

Input Level

ADC PARAMETERS

INL

DNL

TIMING INFORMATION

Chip Enabled to Regulator Ready

Chip Enabled to RSSI Ready

Tx to Rx Turnaround Time

3.625

3.625

ADF7021

Typ

Max Unit

Test Conditions

27

dB

IF filter BW setting = 12.5 kHz, 18.75 kHz, 25 kHz

50

dB

Desired signal 3 dB above the input sensitivity

level, CW interferer power level

55

dB

Increased until BER = 10−3, image channel

excluded

35

dB

Image at FRF − 200 kHz

−3

dB

70

dB

Swept from 100 MHz to 2 GHz, measured as

channel rejection

60

68

65

72

12

24 − j60

26 − j63

71 − j128

dB

dB

dB

dB

dBm

Ω

Ω

Ω

Desired signal 3 dB above the input sensitivity

level, CW interferer power level

Increased until BER = 10−2

FSK mode, BER = 10−3

FRF = 915 MHz, RFIN to GND

FRF = 868 MHz

FRF = 433 MHz

−110 to −36

±2

±3

150

dBm

dB

dB

μs

See the RSSI/AGC section

65

130

65

−99

−113

128

40

MHz/V

MHz/V

MHz/V

dBc/Hz

dBc/Hz

Hz

μs

902 MHz to 928 MHz band, VCO adjust = 0,

VCO_BIAS_SETTING = 8

860 MHz to 870 MHz band, VCO adjust = 0

433 MHz, VCO adjust = 0

PA = 10 dBm, VDD = 3.0 V, PFD = 24.57 MHz,

FRF = 433 MHz, VCO_BIAS_SETTING = 15

1 MHz offset

From 200 Hz to 20 kHz, FRF = 868 MHz

Measured for a 10 MHz frequency step to

within 5 ppm accuracy, PFD = 20 MHz,

loop bandwidth (LBW) = 50 kHz

TBD MHz

TBD MHz

33

pF

PC board layout and crystal specific

2.1

ms

11.0592 MHz crystal, using 33 pF load capacitors

CMOS

levels

See the Reference Input section

±1

LSB

From 2.3 V to 3.6 V, TA = 25°C

±1

LSB

From 2.3 V to 3.6 V, TA = 25°C

10

3.0

150 μs +

(5 × TBIT)

μs

CREG = 100 nF

ms

See Table 14 for more details

Time to synchronized data out, includes AGC

settling; see AGC Information and Timing

section for more details

Rev. PrI | Page 5 of 44

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