MPC8541VTALD(2006) View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MPC8541VTALD
(Rev.:2006)

PowerQUICC™ III Integrated Communications Processor Hardware Specifications

Freescale Semiconductor 

Ethernet: Three-Speed, MII Management

8.2.4 TBI AC Timing Specifications

This section describes the TBI transmit and receive AC timing specifications.

8.2.4.1 TBI Transmit AC Timing Specifications

Table 24 provides the MII transmit AC timing specifications.

Table 24. TBI Transmit AC Timing Specifications

At recommended operating conditions with LVDD of 3.3 V ± 5%.

Parameter/Condition

Symbol 1

Min

Typ

Max

Unit

GTX_CLK clock period

GTX_CLK duty cycle

GMII data TCG[9:0], TX_ER, TX_EN setup time

GTX_CLK going high

tTTX

—

8.0

—

ns

tTTXH/tTTX

40

—

60

%

tTTKHDV

2.0

—

—

ns

GMII data TCG[9:0], TX_ER, TX_EN hold time from

tTTKHDX

1.0

—

—

ns

GTX_CLK going high

GTX_CLK clock rise and fall time

tTTXR, tTTXF 2,3

—

—

1.0

ns

Notes:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state

)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV

symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data

signals (D) reach the valid state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the

time from tTTX (K) going high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in

general, the clock reference symbol representation is based on three letters representing the clock of a particular

functional. For example, the subscript of tTTX represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

2. Signal timings are measured at 0.7 V and 1.9 V voltage levels.

3. Guaranteed by design.

Figure 11 shows the TBI transmit AC timing diagram.

GTX_CLK

TCG[9:0]

tTTX

tTTXR

tTTXH

tTTXF

tTTXF

tTTKHDV

tTTKHDX

tTTXR

Figure 11. TBI Transmit AC Timing Diagram

MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4

26

Freescale Semiconductor

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