MPC8541VTALD(2006) View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MPC8541VTALD
(Rev.:2006)

PowerQUICC™ III Integrated Communications Processor Hardware Specifications

Freescale Semiconductor 

Ethernet: Three-Speed, MII Management

8.2.4.2 TBI Receive AC Timing Specifications

Table 25 provides the TBI receive AC timing specifications.

Table 25. TBI Receive AC Timing Specifications

At recommended operating conditions with LVDD of 3.3 V ± 5%.

Parameter/Condition

Symbol 1

Min

Typ

Max

Unit

RX_CLK clock period

tTRX

16.0

ns

RX_CLK skew

tSKTRX

7.5

—

8.5

ns

RX_CLK duty cycle

tTRXH/tTRX

40

—

60

%

RCG[9:0] setup time to rising RX_CLK

tTRDVKH

2.5

—

—

ns

RCG[9:0] hold time to rising RX_CLK

RX_CLK clock rise time and fall time

tTRDXKH

1.5

—

—

ns

tTRXR, tTRXF 2,3

0.7

—

2.4

ns

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTRDVKH

symbolizes TBI receive timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the

tTRX clock reference (K) going to the high (H) state or setup time. Also, tTRDXKH symbolizes TBI receive timing (TR) with

respect to the time data input signals (D) went invalid (X) relative to the tTRX clock reference (K) going to the high (H) state.

Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a

particular functional. For example, the subscript of tTRX represents the TBI (T) receive (RX) clock. For rise and fall times,

the latter convention is used with the appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript is

skew (SK) followed by the clock that is being skewed (TRX).

2. Guaranteed by design.

Figure 12 shows the TBI receive AC timing diagram.

RX_CLK1

tTRX

tTRXH

tTRXR

tTRXF

RXD[9:0]

RX_CLK0

tTRDVKH

tSKTRX

Valid Data Valid Data

tTRDXKH

tTRXH

tTRDXKH

tTRDVKH

Figure 12. TBI Receive AC Timing Diagram

MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

27

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