S25FL127S(2005) View Datasheet(PDF) - Cypress Semiconductor
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Description
Manufacturer
S25FL127S Datasheet PDF : 131 Pages
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S25FL127S
Table 3.3 Interface States Summary with HOLD# / IO3 Enabled
Interface State
Power-Off
Low Power Hardware Data
Protection
Power-On (Cold) Reset
Interface Standby
Instruction Cycle (Legacy SPI)
Hold Cycle
Single Input Cycle
Host to Memory Transfer
Single Latency (Dummy) Cycle
Single Output Cycle Memory to
Host Transfer
Dual Input Cycle Host to Memory
Transfer
Dual Latency (Dummy) Cycle
Dual Output Cycle Memory to Host
Transfer
QPP Address Input Cycle Host to
Memory Transfer
Quad Input Cycle Host to Memory
Transfer
Quad Latency (Dummy) Cycle
Quad Output Cycle Memory to Host
Transfer
Legend
Z = no driver - floating signal
HL = Host driving VIL
HH = Host driving VIH
HV = either HL or HH
X = HL or HH or Z
HT = toggling between HL and HH
ML = Memory driving VIL
MH = Memory driving VIH
MV = either ML or MH
VDD
<VCC (low)
<VCC (cut-off)
VCC (min)
VCC (min)
VCC (min)
VCC (min)
VCC (min)
VCC (min)
VCC (min)
VCC (min)
VCC (min)
VCC (min)
VCC (min)
VCC (min)
VCC (min)
VCC (min)
SCK
CS#
X
X
X
X
X
HH
X
HH
HT
HL
HV or HT
HL
HT
HL
HT
HL
HT
HL
HT
HL
HT
HL
HT
HL
HT
HL
HT
HL
HT
HL
HT
HL
HOLD# /
IO3
X
X
X
X
HH
HL
HH
HH
HH
HH
HH
HH
X
HV
X
MV
WP# /
IO2
X
X
X
X
HV
X
X
X
X
X
X
X
X
HV
X
MV
SO /
IO1
Z
Z
Z
Z
Z
X
Z
Z
MV
SI / IO0
X
X
X
X
HV
X
HV
X
X
HV
HV
X
X
MV
MV
X
HV
HV
HV
X
X
MV
MV
3.3.1
Power-Off
When the core supply voltage is at or below the VCC (low) voltage, the device is considered to be powered off. The device does not
react to external signals, and is prevented from performing any program or erase operation.
3.3.2
Low Power Hardware Data Protection
When VCC is less than VCC (cut-off) the memory device will ignore commands to ensure that program and erase operations can not
start when the core supply voltage is out of the operating range.
3.3.3
Power-On (Cold) Reset
When the core voltage supply remains at or below the VCC (low) voltage for tPD time, then rises to VCC (Minimum) the device will
begin its Power On Reset (POR) process. POR continues until the end of tPU. During tPU the device does not react to external input
signals nor drive any outputs. Following the end of tPU the device transitions to the Interface Standby state and can accept
commands. For additional information on POR see Power-On (Cold) Reset on page 31.
Document Number: 001-98282 Rev. *F
Page 22 of 130
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