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S25FL256SDSBFIQ01 View Datasheet(PDF) - Cypress Semiconductor

Part Name
Description
Manufacturer
S25FL256SDSBFIQ01 Datasheet PDF : 144 Pages
First Prev 141 142 143 144
S25FL128S, S25FL256S
Document History Page (Continued)
Document Title: S25FL128S, S25FL256S, 128 Mbit (16 Mbyte), 256 Mbit (32 Mbyte) 3.0V SPI Flash Memory
Document Number: 001-98283
Rev.
ECN No.
Orig. of Submission
Change
Date
Description of Change
*B (cont.)
BWHA
03/22/2012
Device ID and Common Flash Interface (ID-CFI) Address Map:
Updated CFI Alternate Vendor-Specific Extended Query Parameter 0 table
Updated CFI Alternate Vendor-Specific Extended Query Parameter 84h Sus-
pend Commands table
Updated CFI Alternate Vendor-Specific Extended Query Parameter 8Ch Reset
Timing table
Ordering Information: Valid Combinations table: added BHV to Package and
Temperature for Models C0, Do and C1, D1
*C
BWHA 06/13/2012 SDR AC Characteristics: Updated tHO value from 0 Min to 2 ns Min
*D
BWHA 07/12/2012 Global: Promoted data sheet designation from Preliminary to Full Production
Global: 80 MHz DDR Read operation added
Performance Summary: Updated Maximum Read Rates DDR (VIO = VCC =
3V to 3.6V) table. Current Consumption table: added Quad DDR Read 80 MHz.
Migration Notes: FL Generations Comparison table: updated DDR values for
*E
BWHA 12/20/2013 FL-S
SDR AC Characteristics: Updated Clock Timing figure
DDR AC Characteristics: Updated AC Characteristics — DDR Operation table
DDR Output Timing: Updated SPI DDR Data Valid Window figure and Notes
Ordering Information: Added 80 MHz to Speed option. Valid Combinations
table: added DS Speed Option.
SDR AC Characteristics:AC Characteristics (Single Die Package, VIO = VCC
2.7V to 3.6V) table: removed tV min AC Characteristics (Single Die Package,
*F
BWHA 03/17/2014 VIO 1.65V to 2.7V, VCC 2.7V to 3.6V) table: removed tV min
Ordering Information:Fix typo: Add DDR for 80 MHz for the DS Speed option.
Valid Combinations table: Addition of more OPNs.
Global: Added Extended Temperature Range: -40°C to 125°C
SDR AC Characteristics: AC Characteristics (Single Die Package, VIO = VCC
2.7V to 3.6V) table: corrected tSU Min
Configuration Register 1 (CR1): Latency Codes for DDR Enhanced High Per-
formance table: added 80 MHz
DDR Fast Read (DDRFR 0Dh, 4DDRFR 0Eh):
Updated figures:
Continuous DDR Fast Read Subsequent Access (3-byte Address [ExtAdd=0,
*G
BWHA 10/10/2014 EHPLC=11b])
Continuous DDR Fast Read Subsequent Access (4-byte Address [ExtAdd=1],
EHPLC=01b)
Initial Delivery State: ASP Register Content table: removed ASPR Default Val-
ue row FE4Fh
Ordering Information FL128S and FL256S:
Added Extended Temperature Range: -40°C to 125°C
Updated Valid Combinations table
Document Number: 001-98283 Rev. *I
Page 142 of 144

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