IDT7016L12PFI8 View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
Manufacturer
IDT7016L12PFI8 Datasheet PDF : 21 Pages
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IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Truth Table IV — Address BUSY
Arbitration
Inputs
Outputs
Military, Industrial and Commercial Temperature Ranges
CEL CER
AOL-A13L
AOR-A13R
BUSYL(1) BUSYR(1)
Function
X X NO MATCH
H
H
Normal
HX
MATCH
H
H
Normal
XH
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
NOTES:
3190 tbl 17
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT7016 are push-pull, not
open drain outputs. On slaves the BUSYX input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable
inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored whenBUSYL outputs are driving LOWregardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR
outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0 - D8 Left
D0 - D8 Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7016.
2. There are eight semaphore flags written to via I/O0 and read from all I/Os (I/O0 - I/O8). These eight semaphores are addressed by A0 - A2.
e. CE = VIH, SEM = VIL to access the semaphores. Refer to the semaphore Read/Write Truth Table.
3190 tbl 18
Functional Description
The IDT7016 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT7016 has an automatic power down
feature controlled by CE. The CE controls on-chip power down
circuitry that permits the respective port to go into a standby mode
when not selected (CE HIGH). When a port is enabled, access to the
entire memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location
(mail box or message center) is assigned to each port. The left port
interrupt flag (INTL) is asserted when the right port writes to memory
location 3FFE where a write is defined as the CE = R/W = VIL per
Truth Table III. The left port clears the interrupt by an address location
3FFE access when CER =OER =VIL, R/W is a "don't care". Likewise,
the right port interrupt flag (INTR) is asserted when the left port writes
to memory location 3FFF and to clear the interrupt flag (INTR), the
right port must access memory location 3FFF. The message (9 bits)
at 3FFE or 3FFF is user-defined since it is in an addressable SRAM
location. If the interrupt function is not used, address locations 3FFE
and 3FFF are not used as mail boxes but are still part of the random
access memory. Refer to Truth Table III for the interrupt opera-
tion.
6.1462
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