IDT7016L12PFI8 View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
Manufacturer
IDT7016L12PFI8 Datasheet PDF : 21 Pages
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IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Busy Logic
Busy Logic provides a hardware indication that both ports of the
RAM have accessed the same location at the same time. It also
allows one of the two accesses to proceed and signals the other side
that the RAM is “busy”. The BUSY pin can then be used to stall the
access until the operation on the other side is completed. If a write
operation has been attempted from the side that receives a BUSY
indication, the write signal is gated internally to prevent the write from
proceeding.
The use of BUSY logic is not required or desirable for all
applications. In some cases it may be useful to logically OR the
BUSY outputs together and use any BUSY indication as an interrupt
source to flag the event of an illegal or illogical operation. If the write
inhibit function of BUSY logic is not desirable, the BUSY logic can be
disabled by placing the part in slave mode with the M/S pin. Once in
slave mode the BUSY pin operates solely as a write inhibit input pin.
Normal operation can be programmed by tying the BUSY pins
HIGH. If desired, unintended write operations can be prevented to a
port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT7016 RAM in master mode, are
push-pull type outputs and do not require pull up resistors to operate.
If these RAMs are being expanded in depth, then the BUSY
indication for the resulting array requires the use of an external AND
gate.
Width Expansion Busy Logic
Master/Slave Arrays
When expanding an IDT7016 RAM array in width while using
BUSY logic, one master part is used to decide which side of the RAM
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master use the BUSY signal as a write inhibit signal. Thus on the
IDT7016 RAM the BUSY pin is an output if the part is used as a
master (M/S pin = H), and the BUSY pin is an input if the part used
as a slave (M/S pin = L) as shown in Figure 3.
If two or more master parts were used when expanding in width,
a split decision could result with one master indicating BUSY on one
side of the array and another master indicating BUSY on one other
side of the array. This would inhibit the write operations from one port
for part of a word and inhibit the write operations from the other port
for the other part of the word.
The BUSY arbitration, on a master, is based on the chip enable
and address signals only. It ignores whether an access is a read or
write. In a master/slave array, both address and chip enable must
be valid long enough for a BUSY flag to be output from the master
before the actual write pulse can be initiated with the R/W signal.
Failure to observe this timing can result in a glitched internal write
inhibit signal and corrupted data in the slave.
Semaphores
The IDT7016 are extremely fast Dual-Port 16Kx9 Static RAMs
with an additional 8 address locations dedicated to binary sema-
phore flags. These flags allow either processor on the left or right side
of the Dual-Port RAM to claim a privilege over the other processor
for functions defined by the system designer’s software. As an
Military, Industrial and Commercial Temperature Ranges
MASTER
CE
Dual Port
RAM
BUSY (L) BUSY (R)
SLAVE
CE
Dual Port
RAM
BUSY (L) BUSY (R)
BUSY (L)
MASTER
CE
Dual Port
RAM
BUSY (L) BUSY (R)
SLAVE
CE
Dual Port
RAM
BUSY (L) BUSY (R)
BUSY (R)
3190 drw 19
Figure 3. Busy and chip enable routing for both width and depth expansion
with IDT7016 RAMs.
example, the semaphore can be used by one processor to inhibit
the other from accessing a portion of the Dual-Port RAM or any other
shared resource.
The Dual-Port RAM features a fast access time, and both ports
are completely independent of each other. This means that the
activity on the left port in no way slows the access time of the right port.
Both ports are identical in function to standard CMOS Static RAM and
can be read from, or written to, at the same time with the only possible
conflict arising from the simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are
protected against such ambiguous situations and may be used by
the system program to avoid any conflicts in the non-semaphore
portion of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM enable,
and SEM, the semaphore enable. The CE and SEM pins control on-
chip power down circuitry that permits the respective port to go into
standby mode when not selected. This is the condition which is
shown in Truth Table I where CE and SEM are both HIGH.
Systems which can best use the IDT7016 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems
can benefit from a performance increase offered by the IDT7016's
hardware semaphores, which provide a lockout mechanism without
requiring complex programming.
Software handshaking between processors offers the maximum
in system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT7016 does not use its semaphore
flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states are
never incurred in either processor. This can prove to be a major
advantage in very high-speed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are indepen-
dent of the Dual-Port RAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignment method called “Token Passing Allocation.” In this method,
the state of a semaphore latch is used as a token indicating that
shared resource is in use. If the left processor wants to use this
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