CXD2460R View Datasheet(PDF) - Sony Semiconductor
Part Name
Description
Manufacturer
CXD2460R Datasheet PDF : 36 Pages
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CXD2460R
3. Serial data and description of functions
Detailed description
D00
to
D07
CHIP
The serial interface data is loaded to the CXD2460R when D00 and D07 are "1". However, this
assumes that D40 to D47 CHKSUM is satisfied.
D07 D06 D05 D04 D03 D02 D01 D00
Function
1 0 0 0 0 0 0 1 Loading to the CXD2460R
This CTGRY data indicates the functions that the serial interface data controls.
D08
to
D11
CTGRY
D11 D10 D09 D08
0000
0010
0011
0100
Function
Mode control data
Electronic shutter control data
High-speed phase adjustment data (Set all of D12 to D39 to "0".)
System setting data
Input of values other than those listed above is prohibited.
CTGRY: Mode control data
D12
FHIGH
Detailed description
0: Power saving drive mode
1: High-speed drive mode
When FHIGH = 0, the clock input to CKI is immediately frequency divided by 1/2 and loaded
internally.
Mode switching timing
(5 clocks after the fall of HRI just before XSGA is generated)
MCK
CKI
Unstable
FHIGH = 1
FHIGH = 0
Unstable
FHIGH = 1
D13
FINE
The high-speed phases of H1, H2, RG, XSHP, XSHD, XRS, ADCLK and other pulses are always
logically the same phase with respect to MCK.
0: DRAFT mode
1: FINE mode
In FINE mode, image data is taken by the normal Progressive Scan method.
In DRAFT mode, image data is taken by pulse elimination readout. This enables a frame rate
four times that during FINE mode. The mode is switched at the fall of HRI just before XSGA.
Note that the FRO output is also switched accordingly. (DRAFT mode: 267H, FINE mode: 1068H)
D14
NSG
0: Normal operation
1: Readout prohibited mode
In readout prohibited mode, a readout pulse is not added even at the timing when a readout pulse
is added to V2A and V2B (VH value). (V1, V2 and V3 are not modulated.)
The mode is normally switched at the fall of HRI just before the position where the readout pulse
is added.
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