DM9302 View Datasheet(PDF) - Davicom Semiconductor, Inc.

Part Name

Description

Manufacturer

DM9302

10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus

Davicom Semiconductor, Inc. 

DM9302

10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus

6. CONTROL AND STATUS REGISTER SET

The DM9302 implements several control and status

registers (CSR), which can be accessed by the host.

All CSR are set to their default values by power on or

software reset unless specified.

Register

Description

NCR

NSR

TCR

RCR

RSR

ROCR

FCR

EPCR

EPAR

EPDRL

EPDRH

LCCR

PAR

MAR

RXPLLR

RXPLHR

RASR

RACR

VID

CHIPR

TCSCR

RCSCSR

DRIVER

IRQCR

SWITCHCR

VLANCR

DSP1,2

P_INDEX

P_CTRL

P_STUS

P_RATE

P_BW

P_UNICAST

P_MULTI

P_BCAST

P_UNKNWN

P_PRI

VLAN_TAGL

VLAN_TAGH

P_MIB_IDX

MIB_DAT

Network Control Register

Network Status Register

TX Control Register

RX Control Register

RX Status Register

Receive Overflow Counter Register

Flow Control Register

EEPROM & PHY Control Register

EEPROM & PHY Address Register

EEPROM & PHY Low Byte Data Register

EEPROM & PHY High Byte Data Register

Link Change Control Register (0FH)

Processor Port Physical Address Registers

Processor Port Multicast Address Registers

RX Packet Length Low Register

RX Packet Length High Register

RX Additional Status Register

RX Additional Control Register

Vendor ID Registers

CHIP Revision Registers

Transmit Check Sum Control Register

Receive Check Sum Control Status Register

uP Data Bus driving capability Register

IRQ Pin Control Register

Switch Control Register

VLAN Control Register

DSP Control Register I,II

Per Port Control/Status Index Register

Per Port Control Data Register

Per Port Status Data Register

Per Port Ingress and Egress Rate Control Register

Per Port Bandwidth Control Setting Register

Per Port Block Unicast Ports Control Register

Per Port Block Multicast Ports Control Register

Per Port Block Broadcast Ports Control Register

Per Port Block Unknown Ports Control Register

Per Port Priority Queue Control Register

Per Port VLAN Tag Low Byte Register

Per Port VLAN Tag High Byte Register

Per Port MIB counter Index Register

MIB counter Data Register bit 0~7

Preliminary datasheet

DM9302-15-DS-P01

July 30, 2009

Offset

00H

01H

02H

05H

06H

07H

0AH

0BH

0CH

0DH

0EH

0FH

10H-15H

16H-1DH

20H

21H

26H

27H

28H-29H

2CH

31H

32H

38H

39H

52H

53H

58H~59H

60H

61H

62H

66H

67H

68H

69H

6AH

6BH

6DH

6EH

6FH

80H

81H

Default value

after reset

00H

00H

00H

00H

00H

00H

00H

00H

40H

00H

00H

00H

by EEPROM

XXH

00H

00H

00H

00H

0A46H

01H

00H

00H

00H

00H

00H

00H

0000H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

01H

00H

00H

00H

15

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