APA3160A View Datasheet(PDF) - Anpec Electronics
Part Name
Description
Manufacturer
APA3160A Datasheet PDF : 38 Pages
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APA3160A
Function Description
Clock And PLL
The APA3160A is a slave device and receives signals from MCLK, SCLK, and LRCLK. The digital audio processor
(DAP) provides all sample rates and MCLK rates which defined in the clock control register.
The APA3160A checks to verify that SCLK is a particular value of 32fS, 48fS, or 64fS. The DAP only provides a 1×fS
LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections.
Serial Data Interface
Serial data is an input transmitted to SDIN. The PWM outputs are derived from SDIN. Besides, the APA3160A DAP
receives left-justified, right-justified, and I2S serial data formats with 16, 20, or 24 bit.
PWM Section
The APA3160A DAP device is a high power efficiency and high-performance digital audio reproduction. A noise shaper
is used to increase dynamic range and SNR in the audio band. The PWM section receives 24bit PCM data from the
DAP and outputs two BTL PWM audio output channels.
The PWM section has individual channel dc blocking filters that can be enabled and disabled. The low pass filter cutoff
frequency is less than 1Hz. Besides, the PWM section includes individual channel de-emphasis filters for 44.1 and
48 kHz and can be enabled and disabled.
The adjustable maximum modulation limit of PWM section is from 93.8% to 98.4%.
I2C Compatible Serial Control Interface
The APA3160A DAP receives commands from a system controller through an I2C serial control slave interface. The
serial control interface supports both normal-speed 100kHz and high-speed 400kHz operations without waiting
states. As an added feature, even though the MCLK is absent, the interface operates.
For status registers, the serial control interface provides single-byte read and write operations; and for the general
control registers, they associated with the PWM.
Copyright © ANPEC Electronics Corp.
11
Rev. A.6 - Jan., 2013
www.anpec.com.tw
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