DSP56852PB View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56852PB

16-bit Digital Signal Processor

Motorola => Freescale 

Freescale Semiconductor, Inc.

DC Electrical Characteristics

4.2 DC Electrical Characteristics

Table 7. DC Electrical Characteristics

Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Characteristic

Symbol

Min

Typ

Max

Unit

Input high voltage (XTAL/EXTAL)

VIHC

VDDA – 0.8 VDDA VDDA + 0.3

V

Input low voltage (XTAL/EXTAL)

VILC

-0.3

—

0.5

V

Input high voltage

VIH

2.0

—

5.5

V

Input low voltage

VIL

-0.3

—

0.8

V

Input current low (pullups disabled)

IIL

-1

—

1

µA

Input current high (pullups disabled)

IIH

-1

—

1

µA

Output tri-state current low

IOZL

-10

—

10

µA

Output tri-state current high

IOZH

-10

—

10

µA

Output High Voltage at IOH

VOH

VDDIO – 0.7

—

—

V

Output Low Voltage at IOL

VOL

—

—

0.4

V

Output High Current at VOH

IOH

8

—

16

mA

Output Low Current at VOL

IOL

8

—

16

mA

Input capacitance

CIN

—

8

—

pF

Output capacitance

COUT

—

12

—

pF

VDD supply current (Core logic, memories, peripherals)

IDD4

Run 1

Deep Stop2

Light Stop3

—

55

70

mA

—

0.02

2.5

mA

—

3.4

8

mA

VDDIO supply current (I/O circuity)

Run5

Deep Stop2

IDDIO

—

40

50

mA

—

0

300

µA

VDDA supply current (analog circuity)

Deep Stop2

IDDA

—

60

120

µA

Low Voltage Interrupt6

VEI

—

2.5

2.85

V

Low Voltage Interrupt Recovery Hysteresis

VEIH

—

50

—

mV

Power on Reset7

POR

—

1.5

2.0

V

Note: Run (operating) IDD measured using external square wave clock source (fosc = 4MHz) into XTAL. All inputs 0.2V from rail;

no DC loads; outputs unloaded. All ports configured as inputs; measured with all modules enabled. PLL set to 240MHz out.

1. Running Core, performing 50% NOP and 50% FIR. Clock at 120 MHz.

2. Deep Stop Mode - Operation frequency = 4 MHz, PLL set to 4 MHz, crystal oscillator.

3. Light Stop Mode - Operation frequency = 120 MHz, PLL set to 240 MHz, crystal oscillator.

4. IDD includes current for core logic, internal memories, and all internal peripheral logic circuitry.

5. Running core and performing external memory access. Clock at 120 MHz.

6. When VDD drops below VEI max value, an interrupt is generated.

7. Power-on reset occurs whenever the digital supply drops below 1.8V. While power is ramping up, this signal remains

active as long as the internal 2.5V is below 1.8V, no matter how long the ramp up rate is. The internally regulated voltage is

typically 100mV less than VDD during ramp up until 2.5V is reached, at which time it self-regulates.

DSP56852 Technical Data

15

Preliminary

For More Information On This Product,

Go to: www.freescale.com

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