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IDT79R4650-100DP(2000) View Datasheet(PDF) - Integrated Device Technology

Part Name
Description
Manufacturer
IDT79R4650-100DP
(Rev.:2000)
IDT
Integrated Device Technology IDT
IDT79R4650-100DP Datasheet PDF : 25 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
IDT79RC4650™
$&#(OHFWULFDO#&KDUDFWHULVWLFV#³#&RPPHUFLDO2,QGXVWULDO#7HPSHUDWXUH
5DQJH³597983
(VCC=3.3V ± 5%; Commercial TCASE = 0°C to +85°C, Industrial TCASE = -40°C to +85°C)
&ORFN#3DUDPHWHUV³597983
Note: Operation of the RC4650 is only guaranteed with the Phase Lock Loop enabled.
3DUDPHWHU
6\PERO
7HVW#&RQGLWLRQV
597983
4660+]
0LQ 0D[
8QLWV
Pipeline clock Frequency
PClk
50
133
MHz
MasterClock HIGH
tMCHIGH
Transition tMCRise/Fall
3
ns
MasterClock LOW
MasterClock Frequency1
tMCLOW
Transition tMCRise/Fall
3
ns
25
67
MHz
MasterClock Period
tMCP
15
40
ns
Clock Jitter for MasterClock
tJitterIn2
±250
ps
MasterClock Rise Time
tMCRise2
4
ns
MasterClock Fall Time
tMCFall2
4
ns
ModeClock Period
tModeCKP2
256*
ns
tMCP
1. Operation of the RC4650 is only guaranteed with the Phase Lock Loop enabled.
2. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability
3DUDPHWHU
Pipeline clock Frequency
MasterClock HIGH
MasterClock LOW
MasterClock Frequency(5)
MasterClock Period
Clock Jitter for MasterClock
MasterClock Rise Time
MasterClock Fall Time
ModeClock Period
597983
4830+]
597983
4;30+]
597983
5330+]
597983
59:0+]
0LQ 0D[ 0LQ 0D[ 0LQ 0D[ 0LQ
50
150
50
180
50
200
100
3
3
3
3
3
3
25 75
25
90
25
13.3 40
11.1 40
10
±250 —
±250 —
3
2.5
3
2.5
256* —
256* —
tMCP
tMCP
3
3
100 50
40
8
±250 —
2
2
256* —
tMCP
0D[
267
125
20
±250
2
2
256*
tMCP
8QLWV
MHz
ns
ns
MHz
ns
ps
ns
ns
ns
17 of 25
March 28, 2000

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