BU1425AK Datasheet PDF - ROHM Semiconductor

BU1425AK View Datasheet(PDF) - ROHM Semiconductor

Part Name

Description

Manufacturer

BU1425AK

NTSC / PAL digital RGB encoder

ROHM Semiconductor

BU1425AK Datasheet PDF : 32 Pages

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Multimedia ICs

BU1425AK / BU1425AKV

∗ In this mode, the internal clock (BCLK) begins to operate at the same phase as the VCLK input, following the rise

of the RSTB pin (pin 52).

Table 13

Parameter

Data setup time 3S

Data hold time 3H

Sync signal setup time

Sync signal hold time

Symbol

Min.

Typ.

Max.

Tds3S

—

Tds3H

—

Tsd1

—

Tsh1

—

4. Slave mode, doubled clock mode

Encoder slave (pin 33 = L)

Internal clock = 2∗ input clock (pin 53 = L)

VCLK (pin53)

Internal clock

(BCLK)

Input data

(HSY, VSY)

Tsh2

Tsd2

Fig.14

Tds4

∗ In this mode, the internal clock (BCLK) begins to operate at a halved frequency at the rise of the VCLK input, fol-

lowing the rise of the RSTB pin (pin 52). When HSY is input, phase correction is carried out at the falling edge, as

shown in Fig. 14. (In other words, the phase of the internal clock (BCLK) is not determined until HSY is input.)

Table 14

Parameter

Data setup time 4

Sync signal hold time 2

Sync signal setup time 2