NT5SV16M8CT View Datasheet(PDF) - Nanya Technology

Part Name

Description

Manufacturer

NT5SV16M8CT

128Mb Synchronous DRAM

Nanya Technology 

NT5SV32M4CT

NT5SV16M8CT

NT5SV8M16CT

128Mb Synchronous DRAM

Burst Write with Auto-Precharge Interrupted by Read

(Burst Length = 4, CAS Latency = 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK

COMMAND

WRITE A

Auto-Precharge

NOP

CAS latency = 3

tCK3, DQs

DIN A0

DIN A1

NOP

DIN A2

READ B

NOP

NOP

tDAL‡

NOP

NOP

*

DOUT B 0

DOUT B1

NOP

DOUT B 2

* Bank A can be reactivated at completion of tDAL.

‡ tDAL is a function of clock cycle time and speed sort.

See the Clock Frequency and Latency table.

Precharge Command

The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered

when CS, RAS, and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to pre-

charge each bank separately or all banks simultaneously. Three address bits, A10, BS0, and BS1, are used to define which

bank(s) is to be precharged when the command is issued.

Bank Selection for Precharge by Address Bits

A10

LOW

HIGH

Bank Select

BS0, BS1

DON’T CARE

Precharged Bank(s)

Single bank defined by BS0, BS1

All Banks

For read cycles, the Precharge Command may be applied (CAS latency - 1) prior to the last data output. For write cycles, a

delay must be satisfied from the start of the last burst write cycle until the Precharge Command can be issued. This delay is

known as tDPL, Data-in to Precharge delay.

After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be

executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Pre-

charge time (tRP).

REV 1.0

May, 2001

21

© NANYA TECHNOLOGY CORP. All rights reserved.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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