NT5SV16M8CT View Datasheet(PDF) - Nanya Technology

Part Name

Description

Manufacturer

NT5SV16M8CT

128Mb Synchronous DRAM

Nanya Technology 

NT5SV32M4CT

NT5SV16M8CT

NT5SV8M16CT

128Mb Synchronous DRAM

Current State Truth Table (Part 3 of 3)(See note 1)

Current State

Write

Recovering

Write

Recovering

with

Auto Pre-

charge

Refreshing

Mode

Register

Accessing

Command

CS RAS CAS WE BS0,BS1 A11 - A0

Description

LLL L

OP Code

Mode Register Set

LLLH

X

X

Auto or Self Refresh

LLH L

BS

X

Precharge

L LHH

BS Row Address Bank Activate

LHL L

BS

Column Write

LHL H

BS

Column Read

LHHH

X

X

No Operation

HX XX

X

X

Device Deselect

LLL L

OP Code

Mode Register Set

LLLH

X

X

Auto or Self Refresh

LLH L

BS

X

Precharge

L LHH

BS Row Address Bank Activate

LHL L

BS

Column Write

LHL H

BS

Column Read

LHHH

X

X

No Operation

HX XX

X

X

Device Deselect

LLL L

OP Code

Mode Register Set

LLLH

X

X

Auto or Self Refresh

LLH L

BS

X

Precharge

L LHH

BS Row Address Bank Activate

LHL L

BS

Column Write

LHL H

BS

Column Read

LHHH

X

X

No Operation

HX XX

X

X

Device Deselect

LLL L

OP Code

Mode Register Set

LLLH

X

X

Auto or Self Refresh

LLH L

BS

X

Precharge

L LHH

BS Row Address Bank Activate

LHL L

BS

Column Write

LHL H

BS

Column Read

LHHH

X

X

No Operation

HX XX

X

X

Device Deselect

Action

ILLEGAL

ILLEGAL

ILLEGAL

ILLEGAL

Start Write; Determine if Auto Precharge

Start Read; Determine if Auto Precharge

No Operation; Row Active after tDPL

No Operation; Row Active after tDPL

ILLEGAL

ILLEGAL

ILLEGAL

ILLEGAL

ILLEGAL

ILLEGAL

No Operation; Precharge after tDPL

No Operation; Precharge after tDPL

ILLEGAL

ILLEGAL

ILLEGAL

ILLEGAL

ILLEGAL

ILLEGAL

No Operation; Idle after tRC

No Operation; Idle after tRC

ILLEGAL

ILLEGAL

ILLEGAL

ILLEGAL

ILLEGAL

ILLEGAL

No Operation; Idle after two clock cycles

No Operation; Idle after two clock cycles

Notes

4

4

9

9

4

4

4, 9

4, 9

1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is

being applied to.

2. All Banks must be idle; otherwise, it is an illegal action.

3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mo de is

entered.

4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being refer-

enced by the Current State then the action may be legal depending on the state of that bank.

5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.

6. The minimum and maximum Active time (t RAS) must be satisfied.

7. The RAS to CAS Delay (tRCD ) must occur before the command is given.

8. Column address A10 is used to determine if the Auto Precharge function is activated.

9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.

10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.

REV 1.0

May, 2001

33

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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