DSP56001 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
DSP56001 Datasheet PDF : 64 Pages
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DSP56001 Electrical Characteristics
AC Electrical Characteristics - Reset, Stop, Mode Select and Interrupt Timing
(Vcc = 5.0 Vdc +10%, TJ = -40 to +105° C, CL = 50 pf + 1 TTL Load at 20.5 MHz and 27 MHz)
(Vcc = 5.0 Vdc + 5%, TJ = -40 to +105° C, CL = 50 pf + 1 TTL Load at 33 MHz)
(See Control Figure 1 through 8)
cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles
WS = Number of wait states (1 WS = 1 cyc = 2T) programmed into external bus access
using BCR (WS = 0 - 15)
tch = Clock high period
tcl = Clock low period
Num
Characteristics
20.5 MHz
27 MHz
33 MHz
Unit
Min
Max
Min
Max
Min
Max
9 Delay from RESET Assertion to
Address High Impedance (periodically
—
50
—
38
—
31
ns
sampled and not 100% tested)
10 Minimum Stabilization Duration
Internal Osc. (see Note 1)
External Clock (see Note 2)
75000 cyc
25 c*yc
*
—
—
75000*cyc
25 cyc
*
—
—
75000*cyc
25 cyc
*
—
—
ns
ns
11 Delay from Asynchronous RESET
Deassertion to First External Address
Output (Internal Reset Negation)
8 cyc
*
9 cyc+40
*
8*cyc
9*cyc+31
8*cyc
9*cyc+25 ns
12 Synchronous Reset Setup Time from
RESET Deassertion to Falling Edge of
20
cyc-10
15
cyc-8
13
cyc-7
ns
External Clock
13 Synchronous Reset Delay Time from
the Synchronous Falling Edge of Exter-
nal Clock to the First External Address
8 cyc+5
*
8 cyc+30
*
8*cyc+5
8*cyc+23
8*cyc+5
8*cyc+19
ns
Output
14 Mode Select Setup Time
100
—
77
—
62
—
ns
15 Mode Select Hold Time
0
—
0
0
ns
16 Edge-Triggered Interrupt Request
16a
assertion
25
15
—
—
17
10
—
—
16
10
—
ns
—
ns
deassertion
RESET
9
A0-A15
VIHR
10
11
First Fetch
DSP56001
Control Figure 1. Reset Timing
MOTOROLA
11
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