MT48LC4M8A1TG-10 View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT48LC4M8A1TG-10

SYNCHRONOUS DRAM

Micron Technology 

16 MEG: x4, x8

SDRAM

shown in Figure 7 for CAS latencies of one, two and three;

data element n + 3 is either the last of a burst of four or the

last desired of a longer burst. The Micron 16Mb SDRAM

uses a pipelined architecture and therefore does not

require the 2n rule associated with a prefetch architec-

ture. A READ command can be initiated on any clock

cycle following a previous READ command. Full-speed

random read accesses can be performed to the same

bank, as shown in Figure 8, or each subsequent READ

may be performed to a different bank.

T0

CLK

Figure 7

Consecutive READ Bursts

T1

T2

T3

T4

T5

COMMAND

READ

NOP

NOP

ADDRESS

BANK,

COL n

NOP

READ

NOP

X = 0 cycles

BANK,

COL b

DQ

DOUT

n

CAS Latency = 1

DOUT

n+1

DOUT

n+2

DOUT

n+3

DOUT

b

T0

T1

T2

T3

T4

T5

T6

CLK

COMMAND

READ

NOP

NOP

NOP

READ

NOP

NOP

ADDRESS

BANK,

COL n

X = 1 cycle

BANK,

COL b

DQ

DOUT

n

DOUT

n+1

DOUT

n+2

DOUT

n+3

DOUT

b

CAS Latency = 2

T0

T1

T2

T3

T4

T5

T6

T7

CLK

COMMAND

READ

NOP

NOP

NOP

READ

NOP

NOP

NOP

ADDRESS

BANK,

COL n

BANK,

COL b

X = 2 cycles

DQ

DOUT

n

DOUT

n+1

DOUT

n+2

CAS Latency = 3

NOTE: Each READ command may be to either bank. DQM is LOW.

DOUT

n+3

DOUT

b

DON’T CARE

16 Meg: x4, x8 SDRAM

16MSDRAMx4x8_B.p65 – Rev. 5/98

15

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©1998, Micron Technology, Inc.

Share Link: