MT48LC4M8A1TG-10 View Datasheet(PDF) - Micron Technology
Part Name
Description
Manufacturer
MT48LC4M8A1TG-10 Datasheet PDF : 50 Pages
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T0
CLK
Figure 8
Random READ Accesses
T1
T2
T3
T4
16 MEG: x4, x8
SDRAM
COMMAND
READ
READ
READ
READ
NOP
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DQ
DOUT
n
CAS Latency = 1
DOUT
a
DOUT
x
DOUT
m
T0
T1
T2
T3
CLK
T4
T5
COMMAND
READ
READ
READ
READ
NOP
NOP
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DQ
DOUT
n
DOUT
a
DOUT
x
CAS Latency = 2
DOUT
m
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
READ
READ
READ
NOP
NOP
NOP
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DQ
DOUT
n
DOUT
a
CAS Latency = 3
NOTE: Each READ command may be to either bank. DQM is LOW.
DOUT
x
DOUT
m
DON’T CARE
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
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