MT48LC4M8A1TG-10 View Datasheet(PDF) - Micron Technology
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Description
Manufacturer
MT48LC4M8A1TG-10 Datasheet PDF : 50 Pages
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WRITEs
WRITE bursts are initiated with a WRITE command,
as shown in Figure 13 (A9 is a “Don’t Care” on x8).
The starting column and bank addresses are pro-
vided with the WRITE command and auto precharge is
either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric WRITE commands used in the following illustra-
tions, auto precharge is disabled.
During WRITE bursts, the first valid data-in element
will be registered coincident with the WRITE command.
Subsequent data elements will be registered on each
successive positive clock edge. Upon completion of a
fixed-length burst, assuming no other commands have
been initiated, the DQs will remain High-Z, and any
additional input data will be ignored (see Figure 14). A
full-page burst will continue until terminated. (At the
end of the page, it will wrap to column 0 and continue.)
A fixed-length WRITE burst may be followed by, or
truncated with, a WRITE burst (provided that AUTO
PRECHARGE was not activated), and a full-page WRITE
burst can be truncated with a subsequent WRITE burst.
The new WRITE command can be issued on any clock
following the previous WRITE command, and the data
Figure 13
WRITE Command
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
A0-A9
COLUMN
ADDRESS
(A9 is a “Don’t Care” for x8)
A10
ENABLE AUTO-PRECHARGE
DISABLE AUTO-PRECHARGE
BANK 1
BA
BANK 0
16 MEG: x4, x8
SDRAM
provided coincident with the new command applies to
the new command. An example is shown in Figure 15.
Data n + 1 is either the last of a burst of two or the last
desired of a longer burst. The Micron 16Mb SDRAM uses
a pipelined architecture and therefore does not require
the 2n rule associated with a prefetch architecture. A
WRITE command can be initiated on any clock cycle
Figure 14
WRITE Burst
T0
T1
T2
T3
CLK
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
BANK,
COL n
DQ
DIN
n
DIN
n+1
NOTE: Burst length = 2. DQM is LOW.
Figure 15
WRITE to WRITE
T0
T1
T2
CLK
COMMAND
WRITE
NOP
WRITE
ADDRESS
BANK,
COL n
BANK,
COL b
DQ
DIN
n
DIN
n+1
DIN
b
NOTE: DQM is LOW. Each WRITE command
may be to either bank.
DON’T CARE
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
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