MT48LC4M8A1TG-10 View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT48LC4M8A1TG-10

SYNCHRONOUS DRAM

Micron Technology 

16 MEG: x4, x8

SDRAM

eration that would result from the same fixed-length

burst with auto precharge. The disadvantage of the

PRECHARGE command is that it requires that the com-

mand and address buses be available at the appropriate

time to issue the command; the advantage of the

PRECHARGE command is that it can be used to truncate

fixed-length or full-page bursts. The auto precharge com-

mand does not truncate fixed-length bursts and does not

apply to full-page bursts.

Full-page READ bursts can be truncated with the

BURST TERMINATE command, and fixed-length READ

bursts may be truncated with a BURST TERMINATE

command, provided that auto precharge was not acti-

vated. The BURST TERMINATE command should be

issued x cycles before the clock edge at which the last

desired data element is valid, where x equals the CAS

latency minus one. This is shown in Figure 12 for each

possible CAS latency; data element n + 3 is the last de-

sired data element of a longer burst.

Figure 12

Terminating a READ Burst

T0

T1

T2

T3

T4

T5

T6

CLK

COMMAND

READ

NOP

NOP

NOP

BURST

NOP

TERMINATE

NOP

X = 0 cycles

ADDRESS

BANK,

COL n

DQ

DOUT

n

CAS Latency = 1

DOUT

n+1

DOUT

n+2

DOUT

n+3

T0

T1

T2

T3

T4

T5

T6

CLK

COMMAND

READ

NOP

NOP

NOP

BURST

NOP

TERMINATE

NOP

ADDRESS

BANK,

COL n

X = 1 cycle

DQ

DOUT

n

DOUT

n+1

DOUT

n+2

DOUT

n+3

CAS Latency = 2

T0

T1

T2

T3

T4

T5

T6

T7

CLK

COMMAND

READ

NOP

NOP

ADDRESS

BANK,

COL n

DQ

CAS Latency = 3

NOTE: DQM is LOW.

NOP

BURST

NOP

TERMINATE

NOP

NOP

X = 2 cycles

DOUT

n

DOUT

n+1

DOUT

n+2

DOUT

n+3

DON’T CARE

16 Meg: x4, x8 SDRAM

16MSDRAMx4x8_B.p65 – Rev. 5/98

19

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©1998, Micron Technology, Inc.

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