Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name
A8
(GPIOA0)
A9
(GPIOA1)
A10
(GPIOA2)
A11
(GPIOA3)
A12
(GPIOA4)
A13
(GPIOA5)
A14
(GPIOA6)
A15
(GPIOA7)
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
PS
DS
Pin No.
Type
Description
14
Output
Address Bus—A8–A15 specify the address for external program or data
memory accesses.
13
Input/Output Port A GPIO—These eight General Purpose I/O (GPIO) pins can be individually
programmed as input or output pins.
12
After reset, the default state is Address Bus.
11
10
9
8
7
34
Input/Output Data Bus— D0–D15 specify the data for external program or data memory
35
accesses. D0–D15 are tri-stated when the external bus is inactive.
36
37
38
39
40
41
42
43
44
46
47
48
49
50
29
Output
Program Memory Select—PS is asserted low for external program memory
access.
28
Output
Data Memory Select—DS is asserted low for external data memory access.
56F826 Technical Data, Rev. 14
12
Freescale Semiconductor