DSP56F826PB View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
DSP56F826PB Datasheet PDF : 56 Pages
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Signals and Package Information
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name
SRCK
Pin No.
Type
Description
53
Input/Output SSI Serial Receive Clock (SRCK)—This bidirectional pin provides the serial bit
rate clock for the Receive section of the SSI. The clock signal can be continuous
or gated and can be used by both the transmitter and receiver in synchronous
mode.
(GPIOC2)
Input/Output Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
STD
After reset, the default state is GPIO input.
54
Output
SSI Transmit Data (STD)—This output pin transmits serial data from the SSI
Transmitter Shift Register.
(GPIOC3)
Input/Output Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
STFS
55
Input
After reset, the default state is GPIO input.
SSI Serial Transmit Frame Sync (STFS)—This bidirectional pin is used by the
Transmit section of the SSI as frame sync I/O or flag I/O. The STFS can be used
by both the transmitter and receiver in synchronous mode. It is used to
synchronize data transfer and can be an input or output pin.
(GPIOC4)
Input/Output Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
STCK
After reset, the default state is GPIO input.
56 Input/ Output SSI Serial Transmit Clock (STCK)—This bidirectional pin provides the serial bit
rate clock for the transmit section of the SSI. The clock signal can be continuous
or gated. It can be used by both the transmitter and receiver in synchronous
mode.
(GPIOC5)
Input/Output Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
SCLK
After reset, the default state is GPIO input.
84
Input/Output SPI Serial Clock—In master mode, this pin serves as an output, clocking slaved
listeners. In slave mode, this pin serves as the data clock input.
(GPIOF4)
Input/Output Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
MOSI
After reset, the default state is SCLK.
85
Input/Output SPI Master Out/Slave In (MOSI)—This serial data pin is an output from a
master device and an input to a slave device. The master device places data on
the MOSI line a half-cycle before the clock edge that the slave device uses to
latch the data.
(GPIOF5)
Input/Output Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
56F826 Technical Data, Rev. 14
Freescale Semiconductor
15
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