DSP56F826PB View Datasheet(PDF) - Freescale Semiconductor
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Description
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DSP56F826PB Datasheet PDF : 56 Pages
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Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name
GPIOB0
GPIOB1
GPIOB2
GPIOB3
GPIOB4
GPIOB5
GPIOB6
GPIOB7
GPIOD0
GPIOD1
GPIOD2
GPIOD3
GPIOD4
GPIOD5
GPIOD6
GPIOD7
SRD
Pin No.
Type
Description
66
Input or Port B GPIO—These eight dedicated General Purpose I/O (GPIO) pins can be
67
Output
individually programmed as input or output pins.
68
After reset, the default state is GPIO input.
69
70
71
72
73
74
Input or Port D GPIO—These eight dedicated GPIO pins can be individually
75
Output
programmed as an input or output pins.
76
After reset, the default state is GPIO input.
77
78
79
82
83
51
Input/Output SSI Receive Data (SRD)—This input pin receives serial data and transfers the
data to the SSI Receive Shift Receiver.
(GPIOC0)
Input/Output Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
SRFS
After reset, the default state is GPIO input.
52 Input/ Output SSI Serial Receive Frame Sync (SRFS)—This bidirectional pin is used by the
receive section of the SSI as frame sync I/O or flag I/O. The STFS can be used
only by the receiver. It is used to synchronize data transfer and can be an input
or an output.
(GPIOC1)
Input/Output Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
56F826 Technical Data, Rev. 14
14
Freescale Semiconductor
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