56F8355 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

56F8355

16-Bit Digital Signal Controllers

Freescale Semiconductor 

Architecture Block Diagram

on-board regulator and power and ground signals. They also do not show the multiplexing between

peripherals or the dedicated GPIOs. Please see Part 2, Signal/Connection Descriptions, to see which

signals are multiplexed with those of other peripherals.

Also shown in Figure 1-2 are connections between the PWM, Timer C and ADC blocks. These

connections allow the PWM and/or Timer C to control the timing of the start of ADC conversions. The

Timer C channel indicated can generate periodic start (SYNC) signals to the ADC to start its conversions.

In another operating mode, the PWM load interrupt (SYNC output) signal is routed internally to the Timer

C input channel as indicated. The timer can then be used to introduce a controllable delay before

generating its output signal. The timer output then triggers the ADC. To fully understand this interaction,

please see the 56F8300 Peripheral User Manual for clarification on the operation of all three of these

peripherals.

56F8355 Technical Data, Rev. 17

Freescale Semiconductor

11

Preliminary

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