88E1116R-NNC1 View Datasheet(PDF) - Marvell Semiconductor
Part Name
Description
Manufacturer
88E1116R-NNC1 Datasheet PDF : 16 Pages
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Alaska® 88E1116R Technical Product Brief
Gigabit Ethernet Transceiver
The RGMII interface supports 10/100/1000BASE-T mode of operation.
Table 2: RGMII Interface
64-QFN
Pin #
60
Pin Name
TX_CLK
Pin
Ty p e
I
63
TX_CTRL
I
Description
RGMII Transmit Clock provides a 125 MHz, 25 MHz, or 2.5 MHz reference
clock with ± 50 ppm tolerance depending on speed.
RGMII Transmit Control. TX_EN is presented on the rising edge of TX_CLK.
A logical derivative of TX_EN and TX_ER is presented on the falling edge of
TX_CLK.
62
TXD[3]
I
RGMII Transmit Data.
61
TXD[2]
TXD[3:0] run at double data rate with bits [3:0] presented on the rising edge of
59
TXD[1]
TX_CLK, and bits [7:4] presented on the falling edge of TX_CLK.
58
TXD[0]
In 10/100BASE-T modes, the transmit data nibble is presented on TXD[3:0] on
the rising edge of TX_CLK.
53
RX_CLK
O
RGMII Receive Clock provides a 125 MHz, 25 MHz, or 2.5 MHz reference clock
with ± 50 ppm tolerance derived from the received data stream depending on
speed.
49
RX_CTRL
O
RGMII Receive Control. RX_DV is presented on the rising edge of RX_CLK.
A logical derivative of RX_DV and RX_ER is presented on the falling edge of
RX_CLK.
55
RXD[3]
O
RGMII Receive Data. RXD[3:0] run at double data rate with bits [3:0] presented
54
RXD[2]
on the rising edge of RX_CLK, and bits [7:4] presented on the falling edge of
51
RXD[1]
RX_CLK.
50
RXD[0]
In 10/100BASE-T modes, the receive data nibble is presented on RXD[3:0] on
the rising edge of RX_CLK.
Doc. No. MV-S105539-00, Rev. --
Page 8
Document Classification: Proprietary Information
Copyright © 2011 Marvell
May 9, 2011, Advance
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