ADSP-21363SBBC-ENG View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-21363SBBC-ENG

SHARC® Processor

Analog Devices 

Preliminary Technical Data

ADSP-21363

Reset

Table 12. Reset

Parameter

Min

Max

Unit

Timing Requirements

tWRST1

RESET Pulse Width Low

4tCK

ns

tSRST

RESET Setup Before CLKIN Low

8

ns

1 Applies after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 100 µs while RESET is low, assuming

stable VDD and CLKIN (not including start-up time of external clock oscillator).

CLKIN

RESET

tWRST

tSRST

Figure 9. Reset

Interrupts

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0,

IRQ1, and IRQ2 interrupts. Also applies to DAI_P20–1 pins

when configured as interrupts

Table 13. Interrupts

Parameter

Timing Requirement

tIPW

IRQx Pulse Width

Min

2 × tPCLK + 2

Max

Unit

ns

DAI_P20-1

FLAG2-0

(IRQ2-0)

tIPW

Figure 10. Interrupts

Rev. PrA | Page 19 of 44 | September 2004

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