ADSP-21363SBBC-ENG View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-21363SBBC-ENG

SHARC® Processor

Analog Devices 

ADSP-21363

Core Timer

The following timing specification applies to FLAG3 when it is

configured as the core timer (CTIMER).

Table 14. Core Timer

Parameter

Switching Characteristic

tWCTIM

CTIMER Pulse Width

Min

4 × tPCLK – 1

Preliminary Technical Data

Max

Unit

ns

FLAG3

(CTIMER)

tW CT IM

Figure 11. Core Timer

Timer PWM_OUT Cycle Timing

The following timing specification applies to Timer0, Timer1,

and Timer2 in PWM_OUT (pulse width modulation) mode.

Timer signals are routed to the DAI_P20–1 pins through the

SRU. Therefore, the timing specifications provided below are

valid at the DAI_P20–1 pins.

Table 15. Timer PWM_OUT Timing

Parameter

Min

Max

Unit

Switching Characteristic

tPWMO

Timer Pulse Width Output

2 tPCLK – 1

2(231 – 1) tPCLK

ns

DAI_P20-1

(TIMER2-0)

tP W MO

Figure 12. Timer PWM_OUT Timing

Rev. PrA | Page 20 of 44 | September 2004

Share Link: