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CS7620 View Datasheet(PDF) - Cirrus Logic

Part Name
Description
Manufacturer
CS7620
Cirrus-Logic
Cirrus Logic Cirrus-Logic
CS7620 Datasheet PDF : 70 Pages
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CS7620
The open-loop transfer function of the black level
adjustment loop is
H(z) = -K-----×-----n--
z1
K
=
----1----
256
blk_gain
blk_gain = 1, 2, 4, or 8
For a fixed gain of 4:
τ
=
-------------1--------------
ln
1
n---2-K---
 f--1-u- 
where blk_gain is programmable through a register
and n = # of black pixels during clamp time, which
is also programmable. The value of Kxn will deter-
mine the open-loop gain of the system. The settling
time for the loop can be calculated using the fol-
lowing formula:
For offset range=1 (reg 06h, bit 0)
τ
=
-l--n---(---1----1-----n---K-----)
f--1-u-
For offset range =0
τ
=
-------------1--------------
ln
1
n---2-K---
 f--1-u- 
During fixed gain mode the time constant is a little
different.
For a fixed gain of 1:
τ
=
-------------1--------------
ln
1
n---8-K---
 f--1-u- 
For a fixed gain of 2:
τ
=
-------------1--------------
ln
1
n---4-K---
 f--1-u- 
For a fixed gain of 8:
τ
=
 -l--n---(---1----1-----n---K-----)
f--1-u-
In order to achieve no ringing in the settling use,
-n--
K
1
for offset range
= 1, and
---n----
2K
1
for offset
range = 0.
The 9 MSBs of the black level accumulator can be
read or written through a register. If written, the
LSBs are set to zero. The black level is set to “8” in
a 10-bit digital output representation. In a 13-bit
representation, it is set to “64.” The power-up de-
fault value in the accumulator is at mid level.
Also note that the black level adjust loop can be
disabled. In addition, the black level can be pro-
grammed through the serial port.
3.2 Gain Adjust Block
In order to increase the dynamic range of the ADC,
a variable gain, whose value is determined by the
signal level, is applied to each pixel. This allows
for 13 bits of dynamic range and 10 bits of resolu-
tion after accounting for the significance of the
ADC output bits. The gain applied in the analog is
illustrated in the transfer curve in Figure 7. Once
the signal is digitized, the gain adjust block uses the
gain information for a given pixel word and shifts
its bits accordingly. For example, using the default
full scale level of 1.07V, if Vin = 0.3 V, the VGA
would choose a gain of 2X so the ADC input is 0.6
V. The 10-bit output of the ADC (with no black
level) is (0.6/1.07) × 1024 = 574, or “1000111110.”
in binary. The gain adjust block will take this value
12
DS301PP2

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