CS7620 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CS7620

CCD Imager Analog Processor

Cirrus Logic 

CS7620

DAC outputs (these may be powered down through

register control if they are not being used). The sec-

ond signal is the EXPOSE signal. This signal

should go high at the beginning of exposure and

low at the beginning of readout. The suggested tim-

ing of these signals is shown in Figure 16. Note that

the chip must power up at least 500 µs before read-

out begins. The LINE_ENA and CLAMP pins are

not used in this mode.

3.4.2 Horizontal Only Timing Mode

To select this mode, the user must set the

BYPASS_PLL pin low and select external timing

mode in the timing mode register. The CS7620 is

the master of the pixel rate timing, but the line and

frame timing is controlled externally. In this mode,

the user must control four signals- PWR_DN, EX-

POSE, LINE_ENA, and CLAMP. The master

PWR_DN signal may be used to conserve power

during non-readout time. The EXPOSE pin is rede-

fined as the non-readout signal. When high, the

H1-H4 and RG signals are set in their idle state

(low for H1-H4, high for RG). The LINE-ENA pin

should be high during the vertical shift and load pe-

riods. This will hold the H1-H4 signals in their

user-programmable default states. The CLAMP

pin should be high when over dark reference

(black) pixels. The suggested timing for these sig-

nals is shown in Figure 17. Note that the chip

should power up at least 500 µs before the begin-

ning of readout. The CLAMP signal may also be

high during the dark pixel lines at the beginning of

the frame.

SYSTEM_CLK

CLKO (DATA_VALID)

DOUT<9:0>

Figure 15. CS7620 output data and clocks

>500 µs

POWERDOWN SIGNAL

EXPOSE SIGNAL

TEXP

TREADOUT

TFRAME

Figure 16. Picture Signal Timing

WARNING: NOTE: It is recommended to keep the part in power down mode while not in use to reduce power

16

DS301PP2

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