CS7620 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CS7620

CCD Imager Analog Processor

Cirrus Logic 

CS7620

3.4.3 Slave mode

To select this mode, the user must set the

BYPASS_PLL pin high and select external timing

mode in the timing register. The CS7620 timing is

now slaved off of an external source and supplied

with sampling clocks for feedthrough and data. In

this mode, the user must control five signals-

PWR_DN, EXPOSE, CLAMP, CK_FT

(CLOCK_IN), and CK_DT (LINE_ENA). The

master PWR_DN signal may be used to conserve

power during non-readout time. The EXPOSE pin

is redefined as the non-readout signal. Using the

falling edge of this signal, the chip will delay its

RD_OUT pin output by the appropriate amount as

determined by the chip latency so that it will go ac-

tive at the correct point in the data stream. CLAMP

should be high when over the dark reference pixels.

The CLOCK_IN and LINE_ENA pins are rede-

fined as the CK_FT and CK_DT signals, which

sample the feedthrough and data levels, respective-

ly. The suggested timing for PWR_DN, EXPOSE,

and CLAMP is the same as shown previously in

Figures 16 and 17. The timing for CK_FT

(CLOCK-IN) and CK_DT (LINE-ENA) is shown

in Figure 18.

3.4.4 Horizontal Timing Generator

During every horizontal line period the data from

the horizontal shift register is shifted out on the

CCD output pin one pixel at a time. The analog tim-

ing generator creates the required driving signals to

control the CCD horizontal timing as well as the

analog sampling signals. The timing signals in-

volved in this operation are H1, H2, H3, H4 and

RG. The exact timing of these signals can be con-

CLAMP SIGNAL

LINE_ENA SIGNAL

V SHIFT EXTENDED

& LOAD PIXELS

DARK

PIXELS

TLINE

ACTIVE

PIXELS

ACTIVE

PIXELS

Figure 17. Signal Timing for Horizontal Only Mode

V SHIFT

& LOAD

TLINE+1

CCD

INPUT

SIGNAL

CK_FT

CK_DT

Figure 18. Signal Timing for Slave Mode

DS301PP2

17

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