MT48LC128M4A2 View Datasheet(PDF) - Micron Technology
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Description
Manufacturer
MT48LC128M4A2 Datasheet PDF : 68 Pages
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512Mb: x4, x8, x16 SDRAM
Register Definition
Table 4:
Burst Definition
Notes:
Burst Starting Column
Length
Address
Order of Accesses Within a Burst
Type = Sequential
Type = Interleaved
2
4
8
Full
page (y)
–
– A0
–
–
0
–
–
1
– A1 A0
–
0
0
–
0
1
–
1
0
–
1
1
A2 A1 A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
n = A0–A12/11/9
(location 0–y)
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1,
Cn + 2
Cn + 3,
Cn + 4…,
…Cn - 1,
Cn…
0-1
1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not supported
1. For full-page accesses: y = 4,096 (x4); y = 2,048 (x8); y = 1,024 (x16).
2. For BL = 2, A1–A9, A11, A12 (x4); A1–A9, A11 (x8); or A1–A9 (x16) select the block-of-two
burst; A0 selects the starting column within the block.
3. For BL = 4, A2–A9, A11, A12 (x4); A2–A9, A11 (x8); or A2–A9 (x16) select the block-of-four
burst; A0–A1 select the starting column within the block.
4. For BL = 8, A3–A9, A11, A12 (x4); A3–A9, A11 (x8); or A3–A9 (x16) select the block-of-eight
burst; A0–A2 select the starting column within the block.
5. For a full-page burst, the full row is selected and A0–A9, A11, A12 (x4); A0–A9, A11 (x8); or
A0–A9 (x16) select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the following
access wraps within the block.
7. For BL = 1, A0–A9, A11, A12 (x4); A0–A9, A11 (x8); or A0–A9 (x16) select the unique column
to be accessed, and mode register bit M3 is ignored.
CAS Latency (CL)
CL is the delay, in clock cycles, between the registration of a READ command and the
availability of the first piece of output data. The latency can be set to two or three clocks.
If a READ command is registered at clock edge n and the latency is m clocks, the data will
be available by clock edge n + m. The DQs will start driving as a result of the clock edge
one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data
will be valid by clock edge n + m. For example, assuming that the clock cycle time is such
that all relevant access times are met, if a READ command is registered at T0 and the
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
15
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