MT48LC128M4A2 View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT48LC128M4A2

Synchronous DRAM

Micron Technology 

512Mb: x4, x8, x16 SDRAM

Commands

Auto Precharge

Auto precharge is a feature that performs the same individual-bank PRECHARGE func-

tion described above, without requiring an explicit command. This is accomplished by

using A10 to enable auto precharge in conjunction with a specific READ or WRITE

command. A PRECHARGE of the bank/row that is addressed with the READ or WRITE

command is automatically performed upon completion of the READ or WRITE burst,

except in the full-page burst mode, where auto precharge does not apply. Auto precharge

is nonpersistent in that it is either enabled or disabled for each individual READ or

WRITE command.

Auto precharge ensures that the precharge is initiated at the earliest valid stage within a

burst. The user must not issue another command to the same bank until the precharge

time (tRP) is completed. This is determined as if an explicit PRECHARGE command was

issued at the earliest possible time, as described for each burst type in the “Operations”

section on page 20.

BURST TERMINATE

The BURST TERMINATE command is used to truncate either fixed-length or full-page

bursts. The most recently registered READ or WRITE command prior to the BURST

TERMINATE command will be truncated, as shown in the “Operations” section on

page 20. The BURST TERMINATE command does not precharge the row; the row will

remain open until a PRECHARGE command is issued.

AUTO REFRESH

AUTO REFRESH is used during normal operation of the SDRAM and is analogous to

CAS#-BEFORE-RAS# (CBR) REFRESH in conventional DRAMs. This command is

nonpersistent, so it must be issued each time a refresh is required. All active banks must

be PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH

command should not be issued until the minimum tRP has been met after the

PRECHARGE command as shown in the “Operations” section on page 20.

The addressing is generated by the internal refresh controller. This makes the address

bits “Don’t Care” during an AUTO REFRESH command. The 512Mb SDRAM requires

8,192 AUTO REFRESH cycles every 64ms (tREF), regardless of width option. Providing a

distributed AUTO REFRESH command every 7.81µs will meet the refresh requirement

and ensure that each row is refreshed. Alternatively, 8,192 AUTO REFRESH commands

can be issued in a burst at the minimum cycle rate (tRC), once every 64ms.

SELF REFRESH

The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest

of the system is powered down. When in the self refresh mode, the SDRAM retains data

without external clocking. The SELF REFRESH command is initiated like an AUTO

REFRESH command except CKE is disabled (LOW). After the SELF REFRESH command

is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of

CKE, which must remain LOW.

After self refresh mode is engaged, the SDRAM provides its own internal clocking,

causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self

refresh mode for a minimum period equal to tRAS and may remain in self refresh mode

for an indefinite period beyond that.

PDF: 09005aef809bf8f3/Source: 09005aef80818a4a

512MbSDRAM.fm - Rev. L 10/07 EN

19

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2000 Micron Technology, Inc. All rights reserved.

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