MT48LC128M4A2 View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT48LC128M4A2

Synchronous DRAM

Micron Technology 

512Mb: x4, x8, x16 SDRAM

Commands

Commands

Table 6 provides a quick reference of available commands. This is followed by a written

description of each command. Three additional Truth Tables appear in the Operations

section, beginning on page 35; these tables provide current state/next state information.

Table 6:

Truth Table 1 – Commands and DQM Operation

Notes 1–2 apply to entire table; notes appear below

Name (Function)

COMMAND INHIBIT (NOP)

NO OPERATION (NOP)

ACTIVE (Select bank and activate row)

READ (Select bank and column, and start READ burst)

WRITE (Select bank and column, and start WRITE

burst)

BURST TERMINATE

PRECHARGE (Deactivate row in bank or banks)

AUTO REFRESH or SELF REFRESH

(Enter self refresh mode)

LOAD MODE REGISTER

Write enable/output enable

Write inhibit/output High-Z

CS# RAS# CAS# WE# DQM Address

H

X

X

X

X

X

L

H

H

H

X

X

L

L

H

H

X Bank/row

L

H

L

H L/H8 Bank/col

L

H

L

L L/H8 Bank/col

DQs

X

X

X

X

Valid

Notes

3

4

4

L

H

H

L

X

X

Active

L

L

H

L

X

Code

X

5

L

L

L

H

X

X

X

6, 7

L

L

L

L

X Op-code

X

4

–

–

–

–

L

–

Active

8

–

–

–

–

H

–

High-Z 8

Notes:

1. CKE is HIGH for all commands shown except SELF REFRESH.

2. A0–A11 define the op-code written to the mode register, and A12 should be driven LOW.

3. A0–A12 provide row address, and BA0, BA1 determine which bank is made active.

4. A0–A9, A11, A12 (x4); A0–A9, A11 (x8); or A0–A9 (x16) provide column address; A10 HIGH

enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto pre-

charge feature; BA0, BA1 determine which bank is being read from or written to.

5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged

and BA0, BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except

for CKE.

8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock

delay).

COMMAND INHIBIT

The COMMAND INHIBIT function prevents new commands from being executed by the

SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese-

lected. Operations already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM that is

selected (CS# is LOW). This prevents unwanted commands from being registered during

idle or wait states. Operations already in progress are not affected.

PDF: 09005aef809bf8f3/Source: 09005aef80818a4a

512MbSDRAM.fm - Rev. L 10/07 EN

17

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2000 Micron Technology, Inc. All rights reserved.

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