MT48LC128M4A2 View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT48LC128M4A2

Synchronous DRAM

Micron Technology 

512Mb: x4, x8, x16 SDRAM

Operations

Figure 8: Example Meeting tRCD (MIN) when 2 < tRCD (MIN)/tCK ≤ 3

T0

T1

T2

T3

T4

CLK

COMMAND

ACTIVE

NOP

NOP

READ or

WRITE

tRCD

Don’t Care

READs

Figure 9:

READ bursts are initiated with a READ command, as shown in Figure 9.

The starting column and bank addresses are provided with the READ command, and

auto precharge either is enabled or disabled for that burst access. If auto precharge is

enabled, the row being accessed is precharged at the completion of the burst. For the

generic READ commands used in the following illustrations, auto precharge is disabled.

During READ bursts, the valid data-out element from the starting column address will

be available following CL after the READ command. Each subsequent data-out element

will be valid by the next positive clock edge. Figure 10 on page 22 shows general timing

for each possible CL setting.

A subsequent ACTIVE command to another bank can be issued while the first bank is

being accessed, which results in a reduction of total row-access overhead. The minimum

time interval between successive ACTIVE commands to different banks is defined by

tRRD.

READ Command

CLK

CKE HIGH

CS#

RAS#

CAS#

WE#

A0–A9, A11, A12: x4

A0–A9, A11: x8

A0–A9: x16

A12: x8

A11, A12: x16

A10

BA0, BA1

COLUMN

ADDRESS

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

BANK

ADDRESS

Don't Care

PDF: 09005aef809bf8f3/Source: 09005aef80818a4a

512MbSDRAM.fm - Rev. L 10/07 EN

21

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2000 Micron Technology, Inc. All rights reserved.

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