MT48LC128M4A2 View Datasheet(PDF) - Micron Technology
Part Name
Description
Manufacturer
MT48LC128M4A2 Datasheet PDF : 68 Pages
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512Mb: x4, x8, x16 SDRAM
Operations
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 13
shows the case where the clock frequency allows for bus contention to be avoided
without adding a NOP cycle, and Figure 14 shows the case where the additional NOP is
needed.
Figure 13: READ-to-WRITE
T0
T1
T2
T3
T4
CLK
DQM
COMMAND
READ
NOP
NOP
NOP
WRITE
ADDRESS
BANK,
COL n
DQ
BANK,
COL b
tCK
tHZ
DOUT n
DIN b
tDS
Transitioning Data
Don’t Care
Note:
A CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE
command may be to any bank. If a burst of 1 is used, then DQM is not required.
Figure 14: READ-to-WRITE with Extra Clock Cycle
T0
T1
T2
T3
CLK
T4
T5
DQM
COMMAND
READ
NOP
NOP
NOP
NOP
WRITE
ADDRESS
BANK,
COL n
DQ
tHZ
DOUT n
BANK,
COL b
DIN b
tDS
Transitioning Data
Don’t Care
Note:
CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE
command may be to any bank.
A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE
command to the same bank (provided that auto precharge was not activated), and a full-
page burst may be truncated with a PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles before the clock edge at which the last
desired data element is valid, where x = CL - 1. This is shown in Figure 15 on page 26 for
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
25
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