MT48LC128M4A2 View Datasheet(PDF) - Micron Technology
Part Name
Description
Manufacturer
MT48LC128M4A2 Datasheet PDF : 68 Pages
| |||
512Mb: x4, x8, x16 SDRAM
Operations
Figure 18: WRITE Burst
T0
T1
T2
T3
CLK
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
BANK,
COL n
DQ
DIN
n
DIN
n+1
Transitioning Data
Don’t Care
Note: BL = 2. DQM is LOW.
Data for any WRITE burst may be truncated with a subsequent READ command, and
data for a fixed-length WRITE burst may be immediately followed by a READ command.
After the READ command is registered, the data inputs will be ignored, and WRITEs will
not be executed. An example is shown in Figure 21 on page 30. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst.
Figure 19: WRITE-to-WRITE
T0
T1
T2
CLK
COMMAND
WRITE
NOP
WRITE
ADDRESS
BANK,
COL n
BANK,
COL b
DQ
DIN
n
DIN
n+1
Transitioning Data
DIN
b
Don’t Care
Note: DQM is LOW. Each WRITE command may be to any bank.
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
29
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology, Inc. All rights reserved.
Share Link: 