MT48LC128M4A2 View Datasheet(PDF) - Micron Technology
Part Name
Description
Manufacturer
MT48LC128M4A2 Datasheet PDF : 68 Pages
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512Mb: x4, x8, x16 SDRAM
Operations
each possible CL; data element n + 3 is either the last of a burst of four or the last desired
of a longer burst. Following the PRECHARGE command, a subsequent command to the
same bank cannot be issued until tRP is met. Note that part of the row precharge time is
hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvan-
tage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
Full-page READ bursts can be truncated with the BURST TERMINATE command, and
fixed-length READ bursts may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at which the last desired data element is
valid, where x = CL - 1. This is shown in Figure 16 on page 27 for each possible CL; data
element n + 3 is the last desired data element of a longer burst.
Figure 15: READ-to-PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
NOP
NOP
ADDRESS
BANK a,
COL n
t RP
NOP
PRECHARGE
NOP
NOP
X = 1 cycle
BANK
(a or all)
ACTIVE
BANK a,
ROW
DQ
CAS Latency = 2
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
T0
T1
CLK
COMMAND
READ
NOP
ADDRESS
BANK a,
COL n
T2
NOP
T3
T4
T5
T6
t RP
NOP
PRECHARGE
NOP
NOP
BANK
(a or all)
X = 2 cycles
T7
ACTIVE
BANK a,
ROW
DQ
CAS Latency = 3
NOTE: DQM is LOW.
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
TRANSITIONING DATA
DON’T CARE
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
26
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