DSP56002RC40 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56002RC40

24-BIT DIGITAL SIGNAL PROCESSOR

Motorola => Freescale 

Signal/Pin Descriptions

PLL and Clock

Table 1-4 PLL and Clock Signals (Continued)

Signal

Name

PINIT

Signal

Type

Input

State

during

Reset

Signal Description

Input

PLL Initialization Source—The value of this signal at reset defines

the value written into the PLL Enable (PEN) bit in the PLL control

register.

If PINIT is pulled high during reset, the PEN bit is written as a 1,

enabling the PLL and causing the DSP internal clocks to be derived

from the PLL VCO.

If PINIT is pulled low during reset, the PEN bit is written as a 0,

disabling the PLL and causing DSP internal clocks to be derived

from the clock connected to EXTAL.

PLOCK

Output

PEN is written only at the deassertion of RESET and; therefore, the

value of PINIT is ignored after that time.

Indeter-

minate

Phase and Frequency Lock—This output is generated by an

internal Phase Detector circuit. This circuit drives the output high

when:

• the PLL is disabled (the output clock is EXTAL and is

therefore in phase with itself), or

• the PLL is enabled and is locked onto the proper phase

(based on the CKP value) and frequency of EXTAL.

The circuit drives the output low (deasserted) whenever the PLL is

enabled, but has not locked onto the proper phase and frequency.

Note:

PLOCK is a reliable indicator of the PLL lock state only after

the chip has exited the Reset state. During hardware reset,

the PLOCK state is determined by PINIT and the current

PLL lock condition.

1-6

DSP56002/D, Rev. 3

MOTOROLA

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