DSP56002RC40 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56002RC40

24-BIT DIGITAL SIGNAL PROCESSOR

Motorola => Freescale 

Signal/Pin Descriptions

Bus Control

BUS CONTROL

Table 1-7 Bus Control Signals

Signal Signal

Name Type

State

during

Reset

Signal Description

PS

Output Tri-stated Program Memory Select—PS is asserted low for external program

memory access. PS is tri-stated when the BG or RESET signal is

asserted.

DS

Output Tri-stated Data Memory Select—DS is asserted low for external data memory

access. DS is tri-stated when the BG or RESET signal is asserted.

X/Y Output Tri-stated X/Y External Memory Select—This output is driven low during

external Y data memory accesses. It is also driven low during external

exception vector fetches when operating in the Development mode.

X/Y is tri-stated when the BG or RESET signal is asserted.

BS

Output Pulled Bus Select—BS is asserted when the DSP accesses the external bus,

high

and it acts as an early indication of imminent external bus access by

the DSP56002. It may also be used with the bus wait input WT to

generate wait states. BS is pulled high when the BG or RESET signal is

asserted.

BR

Input Input

Bus Request—When the Bus Request input (BR) is asserted, it allows

an external device, such as another processor or DMA controller, to

become the master of the external address and data buses. While the

bus is released, the DSP may continue internal operations using

internal memory spaces. When BR is deasserted, the DSP56002 is the

bus master.When BR is asserted, the DSP56002 will release Port A,

including A0–A15, D0–D23, and the bus control signals (PS, DS, X/Y,

RD, WR, and BS) by placing them in the high-impedance state after

execution of the current instruction has been completed.

Note: To prevent erroneous operation, pull up the BR signal when it

is not in use.

BG

Output Pulled Bus Grant—When this output is asserted, it grants an external

high

device’s request for access to the external bus. This output is

deasserted during hardware reset.

1-8

DSP56002/D, Rev. 3

MOTOROLA

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