DSP56002RC40 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56002RC40

24-BIT DIGITAL SIGNAL PROCESSOR

Motorola => Freescale 

Signal/Pin Descriptions

Interrupt and Mode Control

Table 1-8 Interrupt and Mode Control Signals (Continued)

Signal Name

Signal

Type

State

during

Reset

Signal Description

MODC/NMI Input Input

RESET

Input Input

Mode Select C/Non-maskable Interrupt Request—This input

has two functions:

1. to select the initial chip operating mode, and

2. after internal synchronization, to allow an external

device to request a non-maskable DSP interrupt.

MODC is read and internally latched in the DSP when the

processor exits the Reset state. MODA, MODB, and MODC

select the initial chip operating mode. Several clock cycles

(depending on PLL stabilization time) after leaving the Reset

state, the MODC signal changes to the nonmaskable external

interrupt request NMI. After reset, the chip operating mode

can be changed by software. The NMI input is an external

interrupt request that indicates that an external device is

requesting service. It may be programmed to be level-sensitive

or negative-edge-triggered. If level-sensitive triggering is

selected, an external pull up resistor is required for wired-OR

operation.

Reset—This input is a direct hardware reset on the processor.

When RESET is asserted low, the DSP is initialized and placed

in the Reset state. A Schmitt trigger input is used for noise

immunity. When the RESET signal is deasserted, the initial

chip operating mode is latched from the MODA, MODB, and

MODC signals. The internal reset signal is deasserted

synchronous with the internal clocks. In addition, the PINIT

pin is sampled and written into the PEN bit of the PLL Control

Register and the CKP pin is sampled to determine the polarity

of the CKOUT signal.

MOTOROLA

DSP56002/D, Rev. 3

1-11

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