DSP56002RC40 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56002RC40

24-BIT DIGITAL SIGNAL PROCESSOR

Motorola => Freescale 

Signal/Pin Descriptions

Bus Control

Table 1-7 Bus Control Signals (Continued)

Signal Signal

Name Type

State

during

Reset

Signal Description

BN

Output Pulled Bus Not Required—The BN signal is asserted whenever the chip

low

requires mastership of the external bus. During instruction cycles

where the external bus is not required, BN is deasserted. If the BN

signal is asserted when the DSP is not the bus master, processing has

stopped and the chip is waiting to acquire bus ownership. An external

arbiter may use this signal to help determine when to return bus

ownership to the DSP.

Note: The BN signal cannot be used as an early indication of

imminent external bus access because it is valid later than the

other bus control signals BS and WT.

WT

Input Input

Bus Wait—An external device may insert wait states by asserting WT

during external bus cycles.

Note: To prevent erroneous operation, pull up the WT signal when

it is not in use.

WR Output Tri-stated Write Enable—WR is asserted low during external memory write

cycles. WR is tri-stated when the BG or RESET signal is asserted.

RD

Output Tri-stated Read Enable—RD is asserted low during external memory read

cycles. RD is tri-stated when the BG or RESET signal is asserted.

MOTOROLA

DSP56002/D, Rev. 3

1-9

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