LH28F008SCL-12 View Datasheet(PDF) - Sharp Electronics

Part Name

Description

Manufacturer

LH28F008SCL-12

Flash Memory 8M (1M ×8)

Sharp Electronics 

LHFOSCH3

12

4.1 Read Array Command

Upon initial device power-up and after exit from deep

Dower-down mode, the device defaults to read array

node. This operation is also initiated by writing the

Read Array command. The device remains enabled

‘or reads until another command is written. Once the

nternal WSM has started a block erase, byte write or

ock-bit configuration, the device will not recognize

:he Read Array command until the WSM completes

ts operation unless the WSM is suspended via an

Erase Suspend or Byte Write Suspend command.

The Read Array command functions independently of

:he V,, voltage and RP# can be VI, or V,,.

4.2 Read Identifier Codes Command

The identifier code operation is initiated by writing the

qead Identifier Codes command. Following the

:ommand write, read cycles from addresses shown in

=igure 4 retrieve the manufacturer, device, block lock

:onfiguration and master lock configuration codes

see Table 5 for identifier code values). To terminate

:he operation, write another valid command. Like the

?ead Array command, the Read Identifier Codes

:ommand functions independently of the V,, voltage

lnd RP# can be V,, or V,,. Following the Read

dentifier Codes command, the following information

:an be read:

Table 5. Identifier Codes

*Block is Unlocked

@Block is Locked

*Reserved for Future Use

Master Lock Configuration

*Device is Unlocked

ODevice is Locked

*Reserved for Future Use

4OTE:

. X selects the specific block lock configuration

code to be read. See Figure 4 for the device

identifier code memory map.

4.3 Read Status Register Command

The status register may be read to determine when E

block erase, byte write, or lock-bit configuration i:

complete and whether the operation completec

successfully. It may be read at any time by writing the

Read Status Register command. After writing this

command, all subsequent read operations outpu

data from the status register until another valic

command is written. The status register contents are

latched on the falling edge of OE# or CE#, whichever

occurs. OE# or CE# must toggle to VI, before further

reads to update the status register latch. The Reac

Status Register command functions independently o’

the V,, voltage. RP# can be V,, or V,,.

4.4 Clear Status Register Command

Status register bits SR.5, SR.4, SR.3, and SR.l are

set to “1”s by the WSM and can only be reset by the

Clear Status Register command. These bits indicate

various failure conditions (see Table 7). By allowing

system software to reset these bits, severa

operations (such as cumulatively erasing or locking

multiple blocks or writing several bytes in sequence:

may be performed. The status register may be pollee

to determine if an error occurre during the sequence.

To clear the status register, the Clear Status Register

command (50H) is written. It functions independently

of the applied V,, Voltage. RP# can be VI, or V,,.

This command is not functional during block erase or

byte write suspend modes.

4.5 Block Erase Command

Erase is executed one block at a time and initiated by

a two-cycle command. A block erase setup is first

written, followed by an block erase confirm. This

command sequence requires appropriate sequencing

and an address within the block to be erased (erase

changes all block data to FFH). Block

preconditioning, erase, and verify are handled

internally by the WSM (invisible to the system). After

the two-cycle block erase sequence is written, the

device automatically outputs status register data

when read (see Figure 5). The CPU can detect block

erase completion by analyzing the output data of the

RY/BY# pin or status register bit SR.7.

Rev. 1.0

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