LH28F008SCL-12 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
Manufacturer
LH28F008SCL-12 Datasheet PDF : 49 Pages
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LHF08CH3
23
5 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
The device will often be used in large memory arrays.
SHARP provides three control inputs to
accommodate
multiple memory connections.
Three-line control provides for:
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention will
not occur.
To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs while
deselected memory devices are in standby mode.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
5.2 RY/BY# and Block Erase, Byte Write,
and Lock-Bit Configuration Polling
RY/BY# is a full CMOS output that provides a
hardware method of detecting block erase, byte write
and lock-bit configuration completion. It transitions
low after block erase, byte write, or lock-bit
configuration commands and returns to VOH when
the WSM has finished executing the internal
slgorithm.
RY/BY# can be connected to an interrupt input of the
system CPU or controller. It is active at all times.
RY/BY# is also VOH when the device is in block erase
suspend (with byte write inactive), byte write suspend
or deep power-down modes.
5.3 Power Supply Decoupling
Flash memory power switching characteristics require
careful device decoupling. System designers arc
interested in three supply current issues; standb
current levels, active current levels and transien
peaks produced by falling and rising edges of CEI
and OE#. Transient current magnitudes depend OI
the device outputs’ capacitive and inductive loading
Two-line control and proper decoupling capacito
selection will suppress transient voltage peaks. Eacl
device should have a 0.1 pF ceramic capacito
connected between its V,, and GND and between it:
V,, and GND. These high-frequency, low inductance
capacitors should be placed as close as possible tc
package leads. Additionally, for every eight devices
a 4.7 pF electrolytic capacitor should be placed at thf
array’s power supply connection between V,, ant
GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductance.
5.4 Vpp Trace on Printed Circuit Boards
Updating flash memories that reside in the targe
system requires that the printed circuit boarc
designer pay attention to the V,, Power supply trace
The V,, pin supplies the memory cell current for byte
writing and block erasing. Use similar trace width:
and layout considerations given to the V,, powel
bus. Adequate V,, supply traces and decoupling wil
decrease V,, voltage spikes and overshoots.
Rev. 1.0
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