LH28F008SCL-12 View Datasheet(PDF) - Sharp Electronics

Part Name

Description

Manufacturer

LH28F008SCL-12

Flash Memory 8M (1M ×8)

Sharp Electronics 

SI-IARP

LHF08CH3

24

5.5 Vcc, Vpp, RP# Transitions

Block erase, byte write and lock-bit configuration are

not guaranteed if V,, falls outside of a valid VPPH,,z3

range, V,, falls outside of a valid Vcc,,s range, or

RP##V,H or V,,. If V,, error is detected, status

register bit SR.3 is set to “1” along with SR.4 or SR.5,

depending on the attempted operation. If RP#

transitions to V,, during block erase, byte write, or

lock-bit configuration, RY/BY# will remain low until

the reset operation is complete. Then, the operation

will abort and the device will enter deep power-down.

The aborted operation may leave data partially

altered. Therefore, the command sequence must be

repeated after normal operation is restored. Device

power-off or RP# transitions to V,, clear the status

register.

The CUI latches commands issued by system

software and is not altered by V,, or CE# transitions

or WSM actions. Its state is read array mode upon

Dower-up, after exit from deep power-down or after

Vcc transitions below V,,,.

After block erase, byte write, or lock-bit configuration,

3ven after V,, transitions down to V,,,,, the CUI

must be placed in read array mode via the Read

4rray command if subsequent access to the memory

array is desired.

5.6 Power-Up/Down Protection

The device is designed to offer protection against

sccidental block erasure, byte writing, or lock-bit

:onfiguration during power transitions. Upon

lower-up, the device is indifferent as to which power

supply (V,, or Vcc) powers-up first. Internal circuitry

resets the CUI to read array mode at power-up.

A system designer must guard against spuriou

writes for V,, voltages above VLKO when V,, i!

active. Since both WE# and CE# must be low for (

command write, driving either to V,, will inhibit writes

The CUl’s two-step command sequence architectun

provides added level of protection against datz

alteration.

In-system block lock and unlock capability prevent!

inadvertent data alteration. The device is disablec

while RP#=V,, regardless of its control inputs state.

5.7 Power Dissipation

When designing portable systems, designers mus

consider battery power consumption not only during

device operation, but also for data retention during

system idle time. Flash memory’s nonvolatilio

increases usable battery life because data is retainec

when system power is removed.

In addition, deep power-down mode ensures

extremely low power consumption.even when systerr

power is applied. For example, portable computing

products and other power sensitive applications tha,

use an array of devices for solid-state storage car

consume negligible power by lowering RP# to VI,

standby or sleep modes. If access is again needed

the devices can be read following the tPHQV ant

t,,,, wake-up cycles required after RP# is firs!

raised to V,,. See AC Characteristics- Read Only

and Write Operations and Figures 15, 16 and 17 for

more information.

Rev. 1.0

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