M2V28S20TP View Datasheet(PDF) - Mitsumi

Part Name

Description

Manufacturer

M2V28S20TP

128M Synchronous DRAM

Mitsumi 

SDRAM (Rev. 1.0E)

Jun. '99

MITSUBISHI LSIs

M2V28S20TP-6,-7,-8

M2V28S30TP-6,-7,-7L,-8,-8L

M2V28S40TP-7,-7L,-8,-8L

128M Synchronous DRAM

(4-BANK x 8,388,608-WORD x 4-BIT)

(4-BANK x 4,194,304-WORD x 8-BIT)

(4-BANK x 2,097,152-WORD x 16-BIT)

FUNCTION TRUTH TABLE (continued)

Current State /CS /RAS /CAS /WE Address

Command Action

MODE

H X X XX

REGISTER

SETTING

L H H HX

DESEL NOP (Idle after tRSC)

NOP NOP (Idle after tRSC)

L H H L BA

TBST ILLEGAL

READ /

L H L X BA, CA, A10

ILLEGAL

WRITE

L L H H BA, RA

ACT ILLEGAL

L L H L BA, A10

PRE /

PREA

ILLEGAL

L L L HX

Op-Code,

L L LL

Mode-Add

REFA ILLEGAL

MRS ILLEGAL

ABBREVIATIONS:

H=High Level, L=Low Level, X=Don't Care

BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration

NOTES:

1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.

2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on

the state of that bank.

3. Must satisfy bus contention, bus turn around, write recovery requirements.

4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.

5. ILLEGAL if any bank is not idle.

ILLEGAL = Device operation and/or data-integrity are not guaranteed.

MITSUBISHI ELECTRIC

13

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