M2V28S20TP View Datasheet(PDF) - Mitsumi
Part Name
Description
Manufacturer
M2V28S20TP Datasheet PDF : 52 Pages
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SDRAM (Rev. 1.0E)
Jun. '99
MITSUBISHI LSIs
M2V28S20TP-6,-7,-8
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)
(4-BANK x 2,097,152-WORD x 16-BIT)
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read operation can be interrupted by new read of any bank. Random column access is
allowed READ to READ interval is minimum 1 CLK..
Read Interrupted by Read (BL=4, CL=3)
CLK
Command
READ READ
READ
READ
A0-9
Yi Yj
Yk
Yl
A10
0
0
0
0
A11
BA0,1
00 00
10
01
DQ
Qai0 Qaj0 Qaj1 Qbk0 Qbk1 Qbk2 Qal0 Qal1 Qal2 Qal3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any bank. Random column access is
allowed. In this case, the DQ should be controlled adequately by using the DQM to prevent the bus
contention. The output is disabled automatically 1 cycle after WRITE assertion.
Read Interrupted by Write (BL=4, CL=3)
CLK
Command
READ
Write
A0-9
Yi
Yj
A10
0
0
A11
BA0,1
00
00
DQM
Q
Qai0
D
Daj0 Daj1 Daj2 Daj3
DQM control Write control
MITSUBISHI ELECTRIC
21
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