M2V28S20TP View Datasheet(PDF) - Mitsumi

Part Name

Description

Manufacturer

M2V28S20TP

128M Synchronous DRAM

Mitsumi 

SDRAM (Rev. 1.0E)

Jun. '99

MITSUBISHI LSIs

M2V28S20TP-6,-7,-8

M2V28S30TP-6,-7,-7L,-8,-8L

M2V28S40TP-7,-7L,-8,-8L

128M Synchronous DRAM

(4-BANK x 8,388,608-WORD x 4-BIT)

(4-BANK x 4,194,304-WORD x 8-BIT)

(4-BANK x 2,097,152-WORD x 16-BIT)

AUTO REFRESH

Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H)

command. The refresh address is generated internally. 4096 REFA cycles within 64ms refresh

128Mbit memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an

auto-refresh, all banks must be in the idle state. Auto-refresh to auto-refresh interval is minimum tRC.

Any command must not be supplied to the device before tRC from the REFA command.

CLK

/CS

/RAS

/CAS

/WE

CKE

A0-11

BA0,1

Auto-Refresh

NOP or DESELECT

minimum tRC

Auto Refresh on All Banks

Auto Refresh on All Banks

MITSUBISHI ELECTRIC

25

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